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Active Keyword: SoC Machine Learning Design Engineer Remove filter Clear all

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SoC Machine Learning Design Engineer

Apple Inc

Cupertino, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
Machine Learning Generative AI PyTorch TensorFlow JAX MLX Verilog SystemVerilog VHDL UVM RAG Deep Neural Networks Reinforcement Learning Static Timing Analysis CDC RDC Data Structures Algorithms
10+ yrs exp
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SoC Machine Learning Design Engineer

Apple Inc

Austin, TX 21 days ago
Actively hiring Confirmed live today Trusted
Machine Learning Generative AI PyTorch TensorFlow JAX MLX RAG Deep Neural Networks Reinforcement Learning Verilog SystemVerilog VHDL UVM Static Timing Analysis CDC RDC Algorithms Data Structures
10+ yrs exp
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SoC Machine Learning Design Engineer

Apple Inc

Cupertino, CA 21 days ago $150,400–$277,600
Actively hiring Confirmed live today Trusted Competitive pay
Machine Learning Generative AI PyTorch TensorFlow JAX MLX RAG Verilog SystemVerilog VHDL UVM Static Timing Analysis CDC RDC Reinforcement Learning Deep Neural Networks Data Structures Algorithms
3+ yrs exp
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SoC Machine Learning Design Engineer

Apple Inc

Austin, TX 21 days ago
Actively hiring Confirmed live today Trusted
Machine Learning Generative AI PyTorch TensorFlow JAX MLX RAG Deep Neural Networks Reinforcement Learning Verilog SystemVerilog VHDL UVM Static Timing Analysis CDC RDC Algorithms Data Structures
3+ yrs exp
Save

SoC Machine Learning Design Engineer

Apple Inc

Cupertino, CA 124 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
Machine Learning Generative AI PyTorch TensorFlow JAX MLX Verilog SystemVerilog VHDL UVM RAG Deep Neural Networks Reinforcement Learning Static Timing Analysis CDC RDC Data Structures Algorithms
10+ yrs exp
Save

SoC Machine Learning Design Engineer

Apple Inc

Austin, TX 124 days ago
Actively hiring Confirmed live today Low trust
Machine Learning Generative AI PyTorch TensorFlow JAX MLX RAG Deep Neural Networks Reinforcement Learning Verilog SystemVerilog VHDL UVM Static Timing Analysis CDC RDC Algorithms Data Structures
10+ yrs exp
Save