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RTL Verification Mixed-Signal Simulation Python Verilog SPICE PCB Design Analog Simulation SOC Mixed-Signal Simulation PrimeSim System Validation Pre-silicon Verification ASIC FPGA System Design Flows +9 more Show less

RTL Verification Verilog Python Simulation HSPICE PrimeSim PCB Design ASIC FPGA System Validation Pre-silicon Verification System Design Flows +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification +9 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

Systems Engineering V&V MIL-STD-810 MIL-STD-461 MIL-STD-464 MIL-STD-704 DO-160 Jama DOORS Polarion Confluence Excel Requirements Traceability V-model AS9100 +10 more Show less

Ethernet InfiniBand Linux Python Bash Kubernetes KVM HyperV VMware OpenStack NAS SAN Virtualization +8 more Show less