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SystemVerilog UVM Verilog VHDL Python C++ C Perl TCL Linux Verdi DVE Questa JasperGold VLSI Design Digital Design Formal Verification Functional Coverage Assertion-Based Verification GPU Architecture +15 more Show less

RTL Design HDL SystemVerilog Verilog VHDL UVM Digital Design VLSI Design Synthesis Static Timing Analysis STA Computer Architecture SoC SRAM Design Physical Design P&R Timing Closure Python C++ C Perl TCL Linux Testbench Creation Functional Coverage CMOS Transistors Power and Performance Optimization +22 more Show less

VLSI Physical Design Floorplanning Place and Route Static Timing Analysis Clock Tree Synthesis Physical Verification DRC LVS Power Integrity IR Drop Analysis RC Extraction Digital Design Mixed-Signal Design Computer Architecture ICC2 PrimeTime dc_shell Innovus SeaHawk Python C++ C Perl TCL Linux SKILL Make Design Compiler Scheme +25 more Show less

Design for Test (DFT) Digital Design Static Timing Analysis (STA) ATPG Boundary Scan JTA Memory BIST Logic BIST Streaming Scan Network Perl TCL C C++ Python Synopsys TetraMAX Cadence Modus Linux +13 more Show less

Verilog SystemVerilog VHDL Python Perl TCL Linux MATLAB PCB Board-Level Design Solidworks ProE Creo Catia Unigraphics Oscilloscope Multimeter Logic Analyzer Datacenter Systems MOSFETs +15 more Show less