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Analog/Mixed-Signal Circuit Design PHY Design Verilog HDL EMIR SigEM SoC Architecture Delay Locked Loops Phase Interpolators Delay Lines Duty Cycle Correctors pre silicon verification Design Methodologies +8 more Show less

SERDES FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators DLLs LDO Regulators Switched-Cap Circuits +6 more Show less

SERDES FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators DLLs LDO Regulators Biasing Circuits Switched-Cap Circuits High-Speed Data Converters +8 more Show less

SERDES ADCs DACs FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators Mask Design Bench Evaluation Characterization DLLs LDO Regulators Switched-Cap Circuits +11 more Show less

SERDES ADCs DACs FinFET VerilogA AMS CMOS Spectrum Analyzers Oscilloscopes Signal Generators High-Speed Data Converters DLLs LDO Regulators Switched-Cap Circuits Characterization Bench Evaluation +11 more Show less