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NVLink PCI-Express Ethernet UCIE ASIC RTL Verilog VHDL SystemC UVM Simulation Formal Verification SoC Integration Data Movers Protocol Adaptors Network-on-Chip Arbiters Schedulers High-Speed Connectivity Protocols +14 more Show less

Verilog SystemVerilog VHDL Python Perl RTL SoC ASIC Clock_design Power_related_features Design_verification Simulation Scripting_languages Automation_tools +9 more Show less

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

Python Perl Tcl RTL DFT ASIC SoC Synopsys Cadence Mentor_Graphics SerDes Ethernet CI/CD +8 more Show less

VCS Fusion Compiler PrimeTime Power Compiler (PTPX) DFT Compiler Spyglass Python Perl +3 more Show less

SystemVerilog UVM VMM Perl Python C C++ PCIe USB SATA Simulation Debugging CoverageDrivenVerification AssertionBasedVerification +9 more Show less

Altium Designer Python C MS Office Google Suite MIL-STD DMM Bench top supply Oscilloscope Logic analyzer Spectrum analyzer USB 3.0 10Gb Ethernet RS232 Xilinx FPGAs HDI routing +11 more Show less

Verilog SystemVerilog UVM RTL PCIe Ethernet Custom digital circuit design FFE DFE CTLE CDR offset cancellation Static timing analysis Formal verification tools High-speed SerDes I/O Mixed-signal chip design Mentorship Team leadership Communication skills +14 more Show less