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Senior ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting
3+ yrs exp Hybrid
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CPU Server Physical Design Clock Engineer

Qualcomm

Santa Clara, CA 66 days ago $142,200–$213,400
Actively hiring Confirmed live 2 days ago High trust Competitive pay
SPICE RTL Physical Design PLL Standard Cell Optimization Jitter Analysis Circuit Design Verification Hardware Engineering
2+ yrs exp
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CPU Server Physical Design Clock Engineer

Qualcomm

Austin, TX +1 87 days ago $148,300–$222,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design SPICE RTL Standard Cell Optimization PLL Circuit Design Verification Jitter Measurement Hardware Engineering
4+ yrs exp
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