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32,456 roles

Wireless SOC Design Verification Engineer

Apple Inc

Irvine, CA 2 days ago $175,000–$308,500
Actively hiring Confirmed live today Posted this week High trust Above market
SystemVerilog UVM Formal Verification UPF ASIC PCIe AXI AHB NOC WiFi Bluetooth RTL Post-Silicon Bring-up SOC Integration SPI UART
10+ yrs exp
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ASIC Power Engineer

Apple Inc

San Diego, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Posted this week High trust Below market
PTPX Power Artist UPF Python Perl Shell SoC Architecture Pre-silicon Power Estimation Post-silicon Power Correlation PCIe WiFi UWB Logic Design
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ASIC Power Engineer

Apple Inc

Irvine, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live 2 days ago Posted this week High trust Below market
Low Power Design UPF PTPX Power Artist Python Perl Shell SoC Architecture Pre-silicon Power Estimation Post-silicon Power Correlation PCIe WiFi UWB Logic Design
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ASIC Power Engineer

Apple Inc

Sunnyvale, CA 2 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Posted this week High trust Above market
PTPX Power Artist UPF Python Perl Shell SoC Architecture Pre-silicon Power Estimation Post-silicon Power Correlation PCIe WiFi UWB Logic Design
10+ yrs exp
Save

ASIC Power Engineer

Apple Inc

San Diego, CA 2 days ago $175,000–$308,500
Actively hiring Confirmed live today Posted this week High trust Above market
PTPX Power Artist UPF Python Perl Shell SoC Architecture Pre-silicon Power Estimation Post-silicon Power Correlation PCIe WiFi UWB Logic Design
10+ yrs exp
Save

ASIC Power Engineer

Apple Inc

Irvine, CA 2 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Low Power Design UPF PTPX Power Artist Python Perl Shell SoC Architecture Pre-silicon Power Estimation Post-silicon Power Correlation PCIe WiFi UWB Logic Design
10+ yrs exp
Save

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $129,300–$225,300
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
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Low Power Design Engineer

Apple Inc

San Diego, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Irvine, CA 2 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Posted this week High trust Below market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic System Architecture Power Analysis
Save

Low Power Design Engineer

Apple Inc

Sunnyvale, CA 2 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Posted this week High trust Above market
Verilog ASIC Low Power Design UPF STA CDC RDC Python Perl Shell Power Management Logic Power Analysis System Architecture
10+ yrs exp
Save