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Masters Hardware Design Verification Engineering Co-op/Intern

Amd

San Jose, CA +1 42 days ago $83,200–$124,800
Actively hiring Confirmed live yesterday Trusted Below market
Verilog system Verilog UVM Python C++ Perl C Shell MySQL PHP Linux Unix Windows HDL Simulation Logic Design Oscilloscopes Logic Analyzers
Hybrid

Hardware Verification Intern

Nvidia

Santa Clara, CA 44 days ago
Actively hiring Confirmed live yesterday High trust
SystemVerilog UVM Verilog VHDL Python C++ C TCL Perl Linux VLSI Design Digital Design Formal Verification Assertion-Based Verification Verdi DVE Questa JasperGold Cadence Jasper Simulation Tools

Senior Digital Design Verification Engineer, Hardware

Nvidia

Santa Clara, CA 177 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug
5+ yrs exp