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Active Keyword: CPU Design Timing Engineer Remove filter Location: Santa Clara Remove filter Clear all

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CPU Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 10 days ago $209,300–$313,900
Actively hiring Confirmed live yesterday High trust Above market
STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV
6+ yrs exp
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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 11 days ago $175,600–$263,400
Actively hiring Confirmed live yesterday High trust Competitive pay
STA PrimeTime Tempus TCL Python Perl ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction Physical Design Timing Closure
4+ yrs exp
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CPU Design Timing Engineer

Apple Inc

Santa Clara, CA 15 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Physical Design Logic Synthesis PnR Parasitic Extraction clock-domain crossing Assertion Based Verification
10+ yrs exp
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