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Active Keyword: Senior ASIC Design Engineer Remove filter Location: San Jose Remove filter Clear all

2 of up to 20 (filtered)

Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
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Senior ASIC Design Engineer

Cisco

San Jose, CA 75 days ago
Actively hiring Confirmed live yesterday Trusted
Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating Post Silicon Validation Scripting Micro-architecture Place-and-Route Functional Coverage
7+ yrs exp
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