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Python Perl PCB design Test hardware integration Temperature control systems OSATs HTOL Burn-in NPI HVM RMA processes Yield analysis DPPM reduction High-power environments Complex SOC architectures +10 more Show less

Python C/C++ Linux TCP/IP CI/CD Ixia Spirent NX-OS IOS-XR Ethernet PCIe Kubernetes Docker AWS Grafana Prometheus +11 more Show less

Python Perl C C++ PCIe I2C SPI MDIO Ethernet IETF RFCS High-Speed Networking ASIC Design Flows Digital Design +9 more Show less

Python C++ PyTorch AI LLMs DLRMs system-level architectural research event-driven simulation models high-performance interconnects memory hierarchies performance evaluation design-space exploration communication skills collaboration +9 more Show less

Python Perl C/C++ SystemC AMBA AXI/CHI PCIe ESUN UALink Power Management RTL Design SoC Design Flow Implementation & Verification Computer Architecture Custom ASIC/SoC Projects High-Speed Interface Protocols Design for Debug/Test/Excellence +11 more Show less

Python C++ PyTorch LLMs DLRMs AI system hardware architectures system-level architectural research performance-per-watt metrics architecture requirements and trade-offs high-performance interconnects memory hierarchies cross-functional collaboration quantitative modeling +8 more Show less

Python C++ PyTorch AI system hardware architectures LLMs DLRMs performance-per-watt metrics event-driven simulation models system-level architectural research architecture-level design decisions high-performance interconnects memory hierarchies +7 more Show less

SystemVerilog UVM C/C++ Python Test Readiness Reviews (TRRs) SerDes Advanced technology nodes Emulation platforms Hardware-software integration Parameter optimization Equipment metrology Yield enhancement Cross-functional collaboration Technical leadership Mentorship +10 more Show less

LTspice Spice TI WorkBench Cadence Allegro DxDesigner AC Power Integrity Simulation DC Power Integrity Simulation High efficiency DC-DC power conversion Phase and gain margins Power supply layout Thermal design rules Multi-phase power delivery Ultra-low noise power delivery Power-up sequencing PCB layout techniques Grounding techniques Low noise etch techniques Technical presentation skills +13 more Show less

Python C/C++ Linux CI/CD ASIC Networking Test Automation Performance Testing Debugging High-Speed Interfaces Traffic Generators Network Test Tools TCP/IP Routing Switching Pandas JMP +12 more Show less

Verilog VHDL Python Tcl PCIe I2C SPI MDC/MDIO Ethernet Gigabit Ethernet Multi-Gigabit Ethernet 10 Gigabit Ethernet 25G Ethernet 100G Ethernet 400G Ethernet 800G Ethernet DRAM CPU PCB设计 硬件调试 系统级测试 软件团队合作 自动机能力 团队协作 沟通技巧 +20 more Show less

Keysight ADS Ansys HFSS Cadence APD SPICE Python Raptor-X MATLAB Vector Network Analysis IBIS 56G PAM4 SerDes HBM UCIe CoWoS EMIB 2.5D ASIC packaging +11 more Show less

PCB Signal Integrity (SI) Tolerance Analysis Materials Selection Plating Validation Testing Mechanical Engineering Electrical Design Thermal Management Liquid Cooling Coolant Cables Cold-Plate Leak Detection Thermal Interface Materials (TIM) Active Cooling Connectors SPC FMEA 8D/Corrective Action Cause-and-Effect Analysis Design of Experiments (DOE) Risk Assessment +16 more Show less

Python Lua Shell C++ CI/CD USB PCIe DDR AWS Kubernetes Docker PostgreSQL MESON Jenkins Git Prometheus Grafana AI/ML +13 more Show less

Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer PLL CDR CTLE DFE FFE FEC IEEE 802.3 OIF specifications Signal integrity DSP Communication systems +19 more Show less

Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer PLL CDR CTLE DFE FFE FEC IEEE 802.3 OIF specifications Signal integrity DSP communication systems +19 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Exceptions Async_Boundaries HDL Digital_Design_Concepts +11 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Constraints Full_Chip_Design Block_Level_Design RTL_Implementation Digital_Design_Concepts +12 more Show less