Hardware Engineer (High-speed IO/Testing) (Onsite)

Cisco

Actively hiring Verified listing
San Jose, CA Posted 10 days ago $152,400–$221,800 / year
View original post Log in to save

At a glance

AI generated

TL;DR

As a Senior High-Speed Interface Engineer at Cisco Silicon One in San Jose, CA, you will join a team dedicated to developing groundbreaking ASICs for data center and enterprise networks. Your role involves leading the support of internal and external customers with high-speed interconnect requests, including feature development and bug fixes. Day-to-day responsibilities include executing electrical characterization testing, supporting validation and compliance activities, collaborating with cross-functional teams to optimize design solutions, and creating automation tools in Python or Matlab. You will need a strong background in high-speed interface systems, lab measurements, and programming skills in Python and C/C++. The position requires expertise in RF components, test equipment, and analog building blocks such as PLLs, CDRs, and FECs, with an understanding of IEEE 802.3 and OIF specifications being a plus.

Skills

Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer PLL CDR CTLE DFE FFE FEC IEEE 802.3 OIF specifications Signal integrity DSP Communication systems

What you'll do

  • Develop and execute electrical characterization testing for high-speed interconnect devices.
  • Support validation and system integration of Silicon One devices in various environments.
  • Evaluate design tradeoffs with ASIC, system, and signal integrity teams to optimize solutions.
  • Create automation tools using Python or Matlab for lab measurements and data processing.
  • Drive methodology development for Cisco’s high-speed solutions across different system cases.

What we're looking for

  • MSEE or BSEE with 5+ years of lab experience in high-speed systems.
  • Hands-on experience with RF components and test equipment for high-speed measurements.
  • Expertise in high-speed interfaces and analog building blocks like PLL, CDR, CTLE, DFE, FFE, FEC.
  • Proficiency in Python and C/C++ programming for automation and analysis tools.
  • Strong debugging skills and ability to work across multiple engineering teams.

Market check

Salary context

This $152,400–$221,800 range sits above 50% of similar postings on FindRole.

Peer median band

$152,000–$231,000

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$154,450–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 103 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.

Most-posted roles

View all roles at Cisco

More like this

Similar roles

Hardware Engineer (High-speed IO/Testing) (Onsite)

Cisco

Remote (Usa-San Jose, US) 10 days ago $152,400–$221,800
Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer PLL CDR CTLE DFE FFE FEC IEEE 802.3 OIF specifications Signal integrity DSP communication systems
Remote

Hardware Engineer (High-speed IO/Testing) (Onsite)

Cisco

Remote (Usa-San Jose, US) 10 days ago $152,400–$221,800
Python C++ Matlab RF components RF cable bias tee DC block sampling scope real-time scope PPG BERT VNA electrical spectrum analyzer PLL CDR CTLE DFE FFE FEC IEEE 802.3 OIF specifications Signal integrity DSP communication systems
Remote

Senior SI/PI Hardware Engineer, Technical Lead (DDR, PCIe) (Onsite)

Cisco

Remote (Usa-San Jose, US) 30 days ago $191,400–$281,400
HFSS ADS MATLAB Cadence PowerSI/DC Allegro Simbeor HSpice ICAT Seasim Power Integrity simulation tools 3-D field solvers VNA TDR Scopes Transmission line theory Channel modeling Signal integrity concepts Electromagnetic theory Coupling mechanisms High-speed DDR links NRZ and PAM4 SerDes PCB development PI analysis
Remote

ASIC Design Engineer (Onsite)

Cisco

Remote (Usa-San Jose, US) 57 days ago $165,000–$241,400
Verilog SystemVerilog RTL ASIC timing closure power optimization clock gating simulation synthesis static timing analysis Tape-out 2.5D fanout technologies high-performance silicon heterogeneous system integration
Remote

Hardware Applications Engineer

Qualcomm

Santa Clara, Ca,Us, US 24 days ago $143,400–$215,000
SoC CPUs GPUs NPUs DSPs Power_architecture PDN_analysis SI/PI_fundamentals USB PCIe CSI DSI PCB_design Python Shell_scripting Linux RTOS Git JIRA Confluence

Hardware Engineer

Cisco

Remote (Usa-Milpitas, US) 24 days ago $135,800–$193,400
Cadence_Concept Allegro SoC CPU_architectures FPGA Oscilloscopes Logic_Analyzers Spectrum_Analyzers Networking_products Cross-functional_teams
Remote