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Allegro Python Perl LTspice Concept PCIe MDIO SPI I2C DDR4 DDR5 FPGAs CPLD Oscilloscopes VNAs Logic analyzers Signal integrity analysis Power delivery networks +13 more Show less

LTspice Spice TI WorkBench Cadence Allegro DxDesigner AC Power Integrity Simulation DC Power Integrity Simulation High efficiency DC-DC power conversion Phase and gain margins Power supply layout Thermal design rules Multi-phase power delivery Ultra-low noise power delivery Power-up sequencing PCB layout techniques Grounding techniques Low noise etch techniques Technical presentation skills +13 more Show less

Verilog VHDL Python Tcl PCIe I2C SPI MDC/MDIO Ethernet Gigabit Ethernet Multi-Gigabit Ethernet 10 Gigabit Ethernet 25G Ethernet 100G Ethernet 400G Ethernet 800G Ethernet DRAM CPU PCB设计 硬件调试 系统级测试 软件团队合作 自动机能力 团队协作 沟通技巧 +20 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Exceptions Async_Boundaries HDL Digital_Design_Concepts +11 more Show less

Synopsys_DC DCG FC Primetime Verilog SystemVerilog TCL Shell Perl SDC STA Clocking Timing_Constraints Full_Chip_Design Block_Level_Design RTL_Implementation Digital_Design_Concepts +12 more Show less