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SystemVerilog ASIC RTL Digital IP Design Logic Synthesis Linting Checks Clock Domain Crossing Low Power Implementation Gate Level Simulation DFT High Speed Parallel Interfaces Design for Test +7 more Show less

Circuits ElectricalEngineering Algorithms Design Automation Python MATLAB Verilog SystemVerilog VHDL Cadence TannerEDAv12 AnsysQ3DExtractor SpiceSimulationTools Git JIRA Confluence CI/CD +13 more Show less

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3 +9 more Show less

VCS Fusion Compiler PrimeTime Power Compiler (PTPX) DFT Compiler Spyglass Python Perl +3 more Show less