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Active Keyword: Design Verification Engineer Remove filter Location: Palo Alto Remove filter Clear all

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Design Verification Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 60 days ago $135,000–$155,000
Actively hiring Confirmed live yesterday Low trust Below market
ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up
1+ yrs exp
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Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 60 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
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Principal Design Verification Engineer

SpaceX

Palo Alto, CA 114 days ago $210,000–$355,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC FPGA UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models
10+ yrs exp
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