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3 of up to 20 (filtered)

Memory System Designer and Place and Route Engineer

Broadcom

Austin, TX 6 days ago $109,700–$175,500
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog RTL Physical Design STA DRC EM/IR Synthesis Python Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts
8+ yrs exp

Memory Design Engineer

Arm Holdings

Austin, TX 56 days ago $130,100–$176,000
Actively hiring Confirmed live today High trust Below market
VLSI Design SRAM Cadence Virtuoso SPICE FastSpice CMOS Layout Perl .tcl Java UNIX Monte-Carlo Physical Verification Circuit Design Memory Architecture AI Tools
2+ yrs exp Hybrid

Senior RTL Design Engineer, DDR/LPDDR Memory Controller

Amd

Austin, TX +2 93 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
RTL Design Verilog SystemVerilog Python Perl Tcl Digital Logic Design Computer Architecture DDR LPDDR EDA Tools Lint CDC Timing Analysis Synthesis Simulation IP Microarchitecture