Technical Lead, Front-End Power Optimization

Cisco

Remote Actively hiring Posted this week Verified listing
San Jose, CA Posted 3 days ago Apply by Sep 30, 2026 $183,800–$263,600 / year
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99+ other roles within 25 mi Near San Jose, CA

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $224k
$154k most similar roles pay here $275k

This role pays more than 77% of similar roles. Most pay $167,525–$223,700 — the shaded band above. At the midpoint, this role pays about $224k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 134 open roles on FindRole.

Listed pay typically runs $168,800–$241,400 across 134 roles with salary data.

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At a glance

TL;DR

The Technical Lead for Power Analysis and Optimization is a senior role within Cisco’s cutting-edge silicon development team, responsible for driving power efficiency across the entire front-end design cycle from microarchitecture to physical implementation. This position requires evaluating ultra-high-bandwidth packet switching microarchitectures, mapping network traffic patterns to identify power inefficiencies, and developing RTL modifications that align with physical constraints to meet aggressive PPA targets. Key skills include experience in RTL design, optimization, and power modeling using tools like PrimePower RTL, along with expertise in high-speed packet switching architectures and advanced FinFET process nodes. The ideal candidate will also have a strong background in Tcl/Python scripting for automating workflows and leading cross-functional teams to solve complex challenges.

Skills

RTL PrimePower Tcl Python FinFET High-speed packet switching CI/CD VLSI Physical Design Clock gating IR drop analysis Post-implementation analysis Cross-functional collaboration Power modeling Power optimization Silicon One

What you'll do

  • Evaluate microarchitecture through first-principles approach to identify power inefficiencies.
  • Develop understanding of RTL design choices' impact on silicon power efficiency.
  • Implement advanced RTL modifications based on traffic flow analysis for optimization.
  • Integrate physical-aware methodologies early in the design cycle for alignment.
  • Utilize power vectors to simulate and analyze production-level network switching workloads.
  • Partner with Physical Design team to propose RTL enhancements based on implementation.

What we're looking for

  • Bachelor’s Degree in Electrical or Computer Engineering with 8+ years of experience.
  • Experience in RTL design, optimization, and power modeling.
  • Proficiency in performing power analysis using PrimePower RTL.
  • Expertise in mapping application-level workloads to microarchitectural features for power reduction.
  • Knowledge of high-speed packet switching architectures and advanced FinFET process nodes.
  • Scripting skills with Tcl/Python for automating power analysis workflows.

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