Staff Engineer, FPGA

Samsung Semiconductor

Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $208k
$149k most similar roles pay here $264k

This role pays more than 66% of similar roles. Most pay $161,500–$217,500 — the shaded band above. At the midpoint, this role pays about $208k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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At a glance

TL;DR · Staff Engineer, FPGA

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As a Staff Engineer in the FPGA team, you will lead the development and optimization of RTL IPs for CXL Type-2 FPGAs, focusing on critical components like the cache controller and command queues. Your day-to-day responsibilities include designing high-speed interfaces, implementing hardware mechanisms to ensure cache coherency between host CPUs and FPGAs, and optimizing RTL code to meet stringent latency and bandwidth requirements. You will collaborate with software engineers to integrate your designs into kernel drivers and user-space libraries, using tools like Xilinx Vivado, Intel Quartus, and simulation platforms such as Questa or VCS for verification. This role requires expertise in SystemVerilog, a deep understanding of AMBA protocols, PCIe, and CXL.cache, along with strong analytical skills to resolve complex hardware issues in a collaborative environment.

Skills

SystemVerilog Verilog RTL Xilinx Vivado Intel Quartus Questa Xcelium VCS AMBA PCIe CXL.cache AXI AXIS FPGA high-performance digital design memory coherency data structures simulation tools logic analyzers protocol analyzers

What you'll do

  • Develop and optimize RTL IPs for CXL Type-2 FPGAs, focusing on the CXL.cache controller.
  • Design high-speed command queue interfaces to efficiently manage host CPU updates to device registers.
  • Implement hardware mechanisms to maintain coherent access between host CPU and FPGA, reducing latency.
  • Optimize RTL to meet strict latency and bandwidth requirements for high-speed operations.
  • Collaborate with software engineers to integrate with kernel drivers and debug complex RTL-to-Host issues.

What we're looking for

  • 10+ years of industry experience in FPGA development or equivalent education and experience.
  • Expertise in SystemVerilog, Verilog, and RTL design tools like Xilinx Vivado and Intel Quartus.
  • Deep understanding of AMBA (AXI/AXIS), PCIe, CXL.cache protocols, and coherent memory systems.
  • Strong computer architecture fundamentals with experience in high-performance digital design.
  • Ability to develop and optimize RTL IPs for CXL Type-2 FPGAs and manage system integration.
  • Proficient in developing SystemVerilog testbenches and simulation models for protocol compliance verification.

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