Senior Debug Engineer, PCIe/CXL, RAS, Memory
Amd
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How this pay compares to similar roles
This role pays more than 78% of similar roles. Most pay $176,043–$217,700 — the blue band above. At the midpoint, this role pays about $223k versus about $197k for comparable roles.
Based on 240 similar postings.
Employer
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has 500 open roles on FindRole.
Listed pay typically runs $172,000–$258,000 across 500 roles with salary data.
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At a glance
The Sr. Debug Engineer - PCIe/CXL, RAS, Memory joins the Server Customer Engineering team to drive customer issues to closure and deliver high-quality technologies. This role involves leading task forces to identify best solutions for failures related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller systems. The engineer will provide validation and debug recommendations, utilizing debug scripts, protocol analyzers, SCAN, and JTAG tools to perform root cause analysis during the bring-up, validation, and production phases of SOC programs. Key technical requirements include expertise in X86 micro architecture, post-silicon validation methodologies, and high-speed test and measurement equipment like scopes. Candidates must possess programming skills in Python, C++, Perl, or Ruby to develop scripts and navigate complex hardware and software design environments.
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Arm Holdings