Senior Debug Engineer, PCIe/CXL, RAS, Memory

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Austin, TXBellevue, WASanta Clara, CA
Salary
$178,400–$267,600 / yr
Posted
1 day ago
Freshness
Confirmed live today
Closes
Oct 28, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $223k
$141k $281k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $176,043–$217,700 — the blue band above. At the midpoint, this role pays about $223k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 500 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 500 roles with salary data.

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At a glance

TL;DR · Senior Debug Engineer, PCIe/CXL, RAS, Memory

The Sr. Debug Engineer - PCIe/CXL, RAS, Memory joins the Server Customer Engineering team to drive customer issues to closure and deliver high-quality technologies. This role involves leading task forces to identify best solutions for failures related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller systems. The engineer will provide validation and debug recommendations, utilizing debug scripts, protocol analyzers, SCAN, and JTAG tools to perform root cause analysis during the bring-up, validation, and production phases of SOC programs. Key technical requirements include expertise in X86 micro architecture, post-silicon validation methodologies, and high-speed test and measurement equipment like scopes. Candidates must possess programming skills in Python, C++, Perl, or Ruby to develop scripts and navigate complex hardware and software design environments.

What you'll do

  • Resolve customer failures related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller technologies.
  • Provide validation and debug recommendations to customers for new features and technical questions.
  • Use debug scripts, protocol analyzers, SCAN, and JTAG tools to identify and root cause customer failures.
  • Debug issues discovered during the bring-up, validation, and production phases of SOC programs.
  • Lead task forces and collaborative efforts with multiple internal teams to identify technical solutions.
  • Develop Python scripts and other programming languages to support debug and validation processes.
  • Analyze high-speed test and measurement equipment data to resolve complex system issues.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Experience in RAS, PCIe, Memory, MCA, CXL, and Micro-Controller related failures.
  • Experience utilizing debug tools such as debug scripts, protocol analyzers, SCAN, and JTAG tools.
  • Experience debugging issues during the process, bring-up, validation, and production phases of SOC programs.
  • 10+ years of total experience inclusive of RAS, PCIe/CXL, MCA/MCE, or Memory validation and debug (preferred).
  • Experience of post silicon validation methodologies (preferred).
  • Experience developing programming languages such as Python scripts (preferred).
  • Experience handling high-speed test and measurement equipment such as protocol analyzers and scopes (preferred).

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