Silicon Engineering Manager

Accenture

Quick summary

Work type
On-site
Location
Austin, TX
Posted
78 days ago

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Similar $199k
$154k most similar roles pay here $249k

This listing doesn't post a salary. Most similar roles pay $165,312–$232,850.

Based on 238 similar postings.

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About Accenture

Accenture is a leading global professional services company specializing in IT, strategy, consulting, and operations, with a strong focus on digital transformation, cloud computing, and artificial intelligence.

Accenture currently has 131 open roles on FindRole.

Listed pay typically runs $94,400–$235,100 across 89 roles with salary data.

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At a glance

TL;DR · Silicon Engineering Manager

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As a Silicon Engineering Manager at Accenture LLP in Austin, TX, you will lead the development of Gate Level Simulation (GLS) TestBench architecture and verification for ASIC designs, driving the definition of test plans and integrating test cases using SystemVerilog, UVM, C, and Python. You will collaborate closely with design engineers to ensure comprehensive RTL functional verification, defining random constraints to generate valid input stimulus during daily regressions. Additionally, you will supervise a team of junior engineers, mentor them, and work with client engineers, vendors, and SoC/SS teams to deliver timely verification requirements using industry-standard tools like VCS, Questa, and Verdi. This role requires expertise in hardware description languages, scripting knowledge in Python and Unix, and the ability to integrate third-party IPs into TestBench while working in a fast-paced environment.

Skills

SystemVerilog UVM Python C Gate Level Simulation VCS Questa Verdi Synopsys Cadence Siemens VIPs YAML NoC AMBA protocols Cache systems

What you'll do

  • - Develop or enhance Gate Level Simulation (GLS) TestBench architecture for ASIC design verification.
  • - Define and drive the creation of comprehensive TestPlans for RTL designs based on specifications.
  • - Integrate functional coverage into TestBenches using Coverage Driven Verification methodology.
  • - Contribute to the development of testcases in C language for CPU transaction verification.
  • - Supervise team execution and ensure timely delivery of functional verification requirements.

What we're looking for

  • Utilizing SystemVerilog and UVM for RTL design verification.
  • Developing testbenches, simulations, and debugging failures in GLS.
  • Defining and integrating functional coverage using Coverage Driven Verification.
  • Scripting expertise with Python, Unix, and YAML for automation tasks.
  • Leading a team of junior engineers and mentoring them effectively.
  • Integrating third-party IPs like Synopsys, Cadence, Siemens VIPs into TestBench.
  • Collaborating across teams in a fast-paced environment to deliver results.

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