Silicon Design and Validation Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $120,000–$192,000 / yr
Posted: 47 days ago
Closes: Oct 17, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k

This role $156k

$108k most similar roles pay here $233k

This role pays less than 78% of similar roles. Most pay $165,200–$216,250 — the shaded band above. At the midpoint, this role pays about $156k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 105 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 103 roles with salary data.

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At a glance

TL;DR · Silicon Design and Validation Engineer

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Broadcom seeks a Senior Silicon Design and Validation Engineer to join its cutting-edge team focused on data center networking. This role involves designing, verifying, and validating analog and mixed-signal high-speed building blocks for ASIC products. Daily tasks include collaborating with cross-functional teams to develop and validate circuits such as TIAs, PLLs, VCOs, and SerDes, using EDA tools and foundry PDKs. The ideal candidate will have expertise in signal integrity, power integrity measurements, and test development, along with experience in advanced packaging architectures like 2.5D/3D. Proficiency in Python or Matlab is essential for debugging and reporting, while knowledge of IEEE standards and high-speed optical interconnects is highly valued.

Skills

Matlab Python EDA PDK SI PI DCO scopes network_analyzers RF_probing optical_I_O electrical_I_O IEEE_standards 2_5D_packaging 3D_packaging signal_integrity power_integrity PLL LDO TIA SerDes CDR control_loops high_speed_design

What you'll do

Design and verify analog and mixed-signal high-speed building blocks for ASIC products.
Validate and characterize control loops such as PLLs and LDOs in high-speed circuits.
Develop and debug test procedures using measurement equipment like DCO and network analyzers.
Perform bench testing and validation of clock generation, timing IPs, and SerDes components.
Correlate and debug signal integrity and power integrity issues for high-speed designs.

What we're looking for

M.Sc. or PhD in Electrical/Computer Engineering with 6+ years of analog/mixed-signal IP design experience.
Expertise in designing, validating, and verifying high-speed data converters, SerDes, and optical I/Os.
Proficiency in EDA tools, foundry PDKs, and signal/power integrity measurements for debugging.
Experience with bench testing and validation of clock generation, timing IPs, and control loops like PLLs.
Strong analytical skills and understanding of advanced packaging (2.5D/3D) architectures.

Remote

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Lead Post-Silicon Validation Engineer

Nvidia

Santa Clara, CA 17 days ago $200,000–$322,000

C++ SystemC DRAM HBM GDDR LPDDR SOC/GPU Post-Silicon Validation Pre-Silicon Development Memory Systems High Speed Interfaces Debugging Tools Process Implementation Methodologies Technical Communication

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