Silicon Design and Validation Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$120,000–$192,000 / yr
Posted
144 days ago
Freshness
Confirmed live yesterday
Closes
Oct 17, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $156k
$107k most similar roles pay here $238k

This role pays less than 78% of similar roles. Most pay $161,250–$216,250 — the shaded band above. At the midpoint, this role pays about $156k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Silicon Design and Validation Engineer

As a Silicon Design and Validation Engineer, you will perform the design, verification, and validation of analog and mixed-signal high-speed building blocks to launch ASIC products for data center networking. Your daily responsibilities involve collaborating with cross-functional teams to develop components such as Trans-Impedance Amplifiers, PLLs, VCOs, clocking circuitry, and data converters. You will conduct bench test debug, characterization of control loops like LDOs, and perform signal and power integrity measurements for high-speed designs. The role requires proficiency in Matlab or Python, along with experience using DCO, real-time scopes, and network analyzers. You must possess deep knowledge of optical and electrical high-speed I/O architectures, IEEE standards, and foundry PDK integration. This position addresses critical technical challenges in data converter, SerDes, and optical I/O technologies within the data center networking domain.

What you'll do

  • Design, verify, and validate analog and mixed-signal high-speed building blocks for data center networking.
  • Perform bench test debug and validation of clock generation, timing IPs, and SerDes components.
  • Characterize various control loops including PLLs, LDOs, and other critical circuitry.
  • Conduct signal integrity and power integrity measurements to correlate results and debug high-speed designs.
  • Develop test scripts and reports using Matlab or Python for design validation.
  • Identify design bugs and recommend technical workarounds to ensure product success.
  • Utilize measurement equipment such as oscilloscopes and network analyzers for hardware characterization.

What we're looking for

  • M.Sc. or PhD. in Electrical Engineering or Computer Engineering.
  • 6+ years of experience in analog and mixed signal IP design, verification, and validation for high-speed data converters, SerDes, and data center networking.
  • Experience with design, validation, and verification of analog front-end circuits, TIAs, PLLs, VCOs, and clocking circuitry.
  • Knowledge of development methodologies, design flows including EDA integration, and foundry PDK collateral.
  • Experience with bench test debug and validation of clock generation, data converters, TIAs, modulator drivers, CDR, and SerDes.
  • Deep understanding of signal integrity and power integrity for high-speed designs, including PI and SI measurements.
  • Ability to work with Matlab or Python.
  • Experience with measurement equipment such as DCO, oversampling/real time scopes, and network analyzers.

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