SerDes Micro Architect

Apple Inc

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Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $175,000–$308,500 / yr
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $216k

This role $242k

$159k most similar roles pay here $325k

This role pays more than 65% of similar roles. Most pay $177,548–$254,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $216k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · SerDes Micro Architect

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The SerDes Micro Architect joins the Analog Mixed-Signal team to drive the definition of next-generation IPs. In this role, you will define the microarchitecture of analog mixed-signal IPs with a specific focus on SERDES design. Your daily responsibilities include reviewing firmware code, analog and digital circuits, and verifying that designs meet performance requirements. You will collaborate with silicon evaluation and design verification teams to define expected behavior while leading debug efforts during system bring up and factory test. You will also work with signal integrity engineers to determine system requirements. Key technical competencies include expertise in high-speed SERDES receiver, transmitter, and clocking blocks; adaptation algorithms; information theory; equalizers; timing recovery; and DSP concepts. Proficiency is required in Python, MATLAB, C, or C++ for mixed-signal modeling, alongside familiarity with machine learning and simulation tools.

Skills

SERDES Mixed-Signal DSP Python MATLAB C C++ Firmware Embedded Software Machine Learning Signal Integrity System Design Information Theory Timing Recovery Equalizers

What you'll do

Define the microarchitecture of next-generation analog mixed-signal IPs with a focus on SERDES.
Review firmware code, analog circuits, and digital circuits to ensure they meet performance requirements.
Collaborate with verification teams to define expected behavior for silicon components.
Lead debug efforts during system bring-up and factory testing phases.
Work with signal integrity engineers to determine specific system requirements.
Implement adaptation and optimization algorithms for high-speed receiver, transmitter, and clocking blocks.
Perform mixed-signal modeling using Python, MATLAB, or C/C++.

What we're looking for

Bachelor of Science degree.
Minimum of 10 years of relevant industry experience.
Experience leading the definition of high-speed SERDES receiver, transmitter, and clocking blocks (preferred).
Deep understanding of adaptation/optimization algorithms, communications theory, DSP concepts, and system performance tradeoffs (preferred).
Proficiency in equalizers, timing recovery, and system identification (preferred).
Familiarity with mixed-signal modeling in Python, MATLAB, C, or C++ (preferred).
Familiarity with simulation tools for analog, digital, and/or mixed-signal circuits (preferred).
Experience in firmware, embedded software development, or Machine Learning concepts (preferred).