SerDes Circuit Design Engineer

SerDes Circuit Design Engineer will join the high-speed SerDes team to develop next-generation, high-performance wireline transceivers and system-on-chip intellectual property. The role involves designing and executing state-of-the-art analog mixed-signal circuits for SerDes PHY, including Rx, CDR, Tx, bias generators, high-speed clock generation, low-jitter distribution, and mixed-signal calibration. You will collaborate with cross-functional teams to create block-level specifications, perform transistor-level implementation, and conduct behavioral modeling while driving mask designs. Key technical requirements include experience with advanced CMOS FinFET technology, circuit modeling in SystemVerilog, Matlab, Python, or VerilogAMS, and knowledge of high-speed serial protocols like PCIe, USB, and DP. The role focuses on solving complex challenges in power, performance, and area for 64+ Gbps NRZ and PAM applications while utilizing techniques such as CTLE, DFE, and de-emphasis to ensure high-quality signal integrity.