Senior Quantum Analog Layout Engineer | Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $119,800–$234,700 / yr
Posted: 23 days ago
Closes: Nov 9, 2026

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$106k most similar roles pay here $248k

This role pays more than 50% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

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About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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TL;DR · Senior Quantum Analog Layout Engineer | Microsoft Careers

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As a Senior Quantum Analog Layout Engineer on Microsoft's Quantum 1st Party Hardware ASIC team, you will lead the development of high-performance, low-power IP designs for quantum computing hardware, including interconnectivity solutions and foundational analog circuit blocks. Your responsibilities include executing Schematic-to-GDS layouts across multiple process nodes using Cadence Virtuoso or equivalent tools, coordinating tasks with junior layout team members, and managing external vendors to ensure quality and schedule adherence. You will also support the onboarding and offboarding of contingent staff and vendor partners, contribute to project planning and report generation, and establish methodologies for high-quality execution. This role requires extensive experience in Analog Mask Layout execution, proficiency with EDA tools like Cadence Virtuoso, and hands-on layout expertise with high-performance analog blocks such as VCOs, charge pumps, and ADC/DACs. Knowledge of cryogenic PDKs is preferred to address the unique challenges of quantum hardware operating at extremely low temperatures.

Skills

Cadence Virtuoso EDA tools Synopsys Mentor Graphics Schematic-Driven Layout (SDL) Voltage-Controlled Oscillators (VCOs) charge pumps interpolators bandgap references Phase-Locked Loops (PLLs) Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Low-Dropout Regulators (LDOs) Serializer/Deserializers (SerDes) common-centroid layout matching symmetrical layouts signal shielding dummy devices thermal-aware layouts Electromigration/IR-drop (EM/IR)

What you'll do

Deliver GDS layouts for high-performance IP designs across multiple process nodes using industry best practices.
Develop and execute plans for Analog Mask Layout, coordinating tasks with junior team members.
Implement analog-intensive IPs using Cadence Virtuoso design tools, establishing methodologies for execution.
Direct day-to-day activities of contingent layout staff and vendor partners to ensure quality and schedule adherence.
Support project planning, schedule tracking, and report generation for IP delivery alongside peers.

What we're looking for

10+ years of experience in Analog Mask Layout execution and IP delivery.
5+ years of lead experience coordinating day-to-day tasks for a layout team.
Proficient use of Cadence Virtuoso and other EDA tools for SDL.
Hands-on experience with high-performance analog blocks like VCOs, PLLs, ADCs/DACs.
In-depth knowledge of analog design guidelines for performance, speed, and power.
Ability to coordinate execution with external vendors and contingent staff effectively.
Knowledge of cryogenic Process Design Kits (PDKs) and analog layout techniques.

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