Senior Principal HSIO Architect

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TXSan Diego, CA
Salary
$308,600–$417,500 / yr
Posted
6 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $363k
$120k $449k
below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $163,450–$231,000 — the blue band above. At the midpoint, this role pays about $363k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 112 open roles on FindRole.

Listed pay typically runs $207,800–$281,200 across 112 roles with salary data.

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At a glance

TL;DR · Senior Principal HSIO Architect

JOB TITLE: Senior Principal - HSIO Architect (PCIe, CXL, UA Link) The Senior Principal - HSIO Architect joins the team to define and design innovative on-chip interconnect architectures for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets. This role involves architecting high-speed interconnect subsystems, including PCIe, CXL, and UA Link, while defining coherent and non-coherent communication architectures. Key responsibilities include defining IP roadmaps, leading early customer engagements to shape system requirements, and collaborating with performance, power, and physical design teams to optimize bandwidth and latency. The position requires deep expertise in coherency protocols, hierarchical cache design, and memory expansion. Candidates must utilize skills in heterogeneous compute, security, and caching to integrate Arm IP with high-speed I/O subsystems to meet specific compute and memory performance targets.

What you'll do

  • Architect high-speed interconnect subsystems including PCIe, CXL, and UA Link for coherent and non-coherent communication.
  • Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies.
  • Lead early architecture engagements with customers to shape system requirements and deliver implementation-ready specifications.
  • Optimize PCIe/CXL/UA Link behavior, bandwidth, latency, and system efficiency with performance and physical design teams.
  • Integrate Arm IP and high-speed I/O subsystems into SoC architectures to meet performance targets.
  • Partner with software and firmware teams to optimize end-to-end solutions across hardware and drivers.
  • Perform workload analysis and performance modeling to guide architectural decisions.

What we're looking for

  • Bachelor’s or Master’s degree in Electrical or Computer Engineering (or equivalent).
  • 15+ years of experience in semiconductor architecture, design, or related roles.
  • 15+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
  • Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, and memory expansion.
  • Strong knowledge of heterogeneous compute, subsystem design, security, caching, and memory systems.
  • Demonstrated communication and leadership skills to influence executive stakeholders and multi-functional teams.
  • Ability to thrive in dynamic environments with shifting priorities (preferred).
  • Track record of delivering complex projects on time and to spec (preferred).

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