Senior I/O Subsystem Architect

Nvidia

Confirmed live 2 days ago High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $224,000–$356,500 / yr
Posted: 50 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k

This role $290k

$127k most similar roles pay here $381k

This role pays more than 95% of similar roles. Most pay $154,525–$235,750 — the shaded band above. At the midpoint, this role pays about $290k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior I/O Subsystem Architect

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As a Senior I/O Subsystem Architect on the NVLink chip to chip team, you will serve as a technical leader defining advanced chip interconnects and protocols. You will be responsible for developing initial product requirements, crafting architecture solutions for chip-to-chip communication, and optimizing for performance, area, power, security, and resiliency. Your daily work involves architectural modeling, validation, documentation, and driving implementation across design, verification, firmware, and software teams to shepherd products through the full lifecycle. You will utilize expertise in link layer architecture including transaction, data link, and physical layers while working with technologies such as PCIe, UCIE, CHI, CXL, and AXI. The role focuses on solving complex communication challenges by defining interfaces between NVLink C2C blocks and the rest of the chip to ensure seamless integration across various hardware components.

Skills

NVLink PCIe UCIe CHI CXL AXI I/O Architecture Link Layer Transaction Layer Data Link Layer Physical Layer SoC Firmware

What you'll do

Research and craft architecture solutions for chip-to-chip communication optimized for performance, area, power, security, and resiliency.
Define interfaces and flows between NVLink C2C blocks and other components of the chip.
Perform architectural modeling, validation, definition, and documentation for interconnect technologies.
Drive implementation across design, verification, firmware, and software teams throughout the product lifecycle.
Define system architecture for NVLink-C2C interconnects and their associated software stacks.
Evaluate and trade off technical solutions to meet platform requirements for current and future products.
Lead projects from initial concept through pathfinding, prototyping, and final deployment.

What we're looking for

MS or PhD in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).
10+ years of relevant experience in architecture, design, and verification.
Proven experience in link layer architecture including Transaction, Data link, and Physical layers.
Experience with existing interconnects such as PCIe, UCIE, and Chip to Chip links.
Knowledge of industry standard protocols including CHI, CXL, and AXI.
Ability to define system architecture with NVLink-C2C interconnects and associated software stacks.
Skilled in I/O Architecture with experience shipping multiple projects from concept through product lifecycle.
Experience collaborating with multi-functional teams across IP, SoC, firmware, and physical design.

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