Senior DFT Engineer

Nvidia

Hybrid Actively hiring
Santa Clara, US Posted 86 days ago $136,000–$218,500 / year
View original post Log in to save

At a glance

AI generated

TL;DR

As a Design-for-Test (DFT) Engineer at NVIDIA, you will join a team dedicated to developing innovative solutions for DFT architecture and verification on cutting-edge semiconductor chips. Your responsibilities include implementing advanced test access mechanisms, IO BIST, memory BIST, and scan compression, as well as deploying DFT methodologies for future products. You will collaborate with cross-functional teams and mentor junior engineers in test design and trade-offs. The ideal candidate holds a BSEE or equivalent experience with 5+ years, MSEE with 3+ years, or a PhD in DFT-related fields, demonstrating expertise in scan test plans, fault modeling, ATPG, and verification using vendor tools. Strong programming skills in Perl, Python, or Tcl are desired, along with excellent communication abilities to tackle complex challenges in silicon debug and bring-up on ATE systems.

Skills

Perl Python Tcl DFT BIST ATPG fault simulation vendor tools RTL STA place-n-route power management Silicon debug ATE pattern formats failure processing test program development

What you'll do

  • Develop state-of-the-art test access mechanisms for complex semiconductor chips.
  • Implement IO BIST, memory BIST, and scan compression techniques in designs.
  • Mentor junior engineers on test design methodologies and trade-offs.
  • Define comprehensive scan test plans and fault models for advanced products.
  • Analyze and validate test patterns using vendor tools on multi-million gate designs.

What we're looking for

  • BSEE with 5+ years or MSEE with 3+ years in DFT or related fields.
  • Expertise in defining scan test plans, BIST for memories and IOs, fault modeling.
  • Strong analytical skills for verification and validation of complex designs using vendor tools.
  • Experience in silicon debug and bring-up on ATE with pattern formats understanding.
  • Programming and scripting skills in Perl, Python, or Tcl desired.
  • Excellent written and oral communication skills for rare challenges.

Market check

Salary context

This $136,000–$218,500 range sits above 70% of similar postings on FindRole.

Peer median band

$122,250–$215,000

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$142,400–$187,825

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 801 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 797 roles with salary data.

Most-posted roles

View all roles at Nvidia

More like this

Similar roles

Senior DFT Engineer

Nvidia

Us, Ca, Santa Clara, US 84 days ago $168,000–$264,500
DFT ATPG EDA VLSI ATE Python AI CI/CD Kubernetes AWS Git Jenkins PostgreSQL Mentoring 2.5D_IC 3D_IC Multi-Chiplet_Architecture

DFT Engineer - New College Grad

Nvidia

Us, Ca, Santa Clara, US 17 days ago $116,000–$189,750
Perl Python Tcl DFT BIST ATPG fault simulation RTL design STA place-n-route power analysis Silicon debug ATE pattern formats failure processing test program development

Senior Circuit Design Engineer

Nvidia

Us, Ca, Santa Clara, US 119 days ago $168,000–$264,500
Spice Python Perl Tcl Make RTL Logic Synthesis Verification Auto Place and Route STA PnR DRC LVS Power Gating Multi-Vt Post-Silicon Characterization Custom Circuit Design Semi-Custom Circuit Design

Senior Circuit Design Engineer

Nvidia

Remote (Us, Ca, Santa Clara, US) 16 days ago $168,000–$264,500
Spice Perl Tcl Make RTL Logic Synthesis Verification Place and Route Design-for-test(DFT) Analog Circuit Design Mixed-Signal Analog Block Design Digital Circuit Design Security Attacks Detection Circuits EM/IR Analysis Static Timing Analysis Noise Analysis Loop Stability Analysis Monte-Carlo Analysis
Remote

CPU DFT Engineer

Qualcomm

Santa Clara, Ca,Us, US 21 days ago $142,200–$213,400
Verilog VHDL Mentor Tessent tools TCL Perl Python Shell scripting JTAG ATPG IEEE 1500 Standard MBIST LBIST SOC level verification Test compression software

Senior Electronics Design Engineer

Motorola Solutions

Los Angeles, Ca, US 60 days ago $120,000–$180,000
Altium Designer Python MATLAB C Xilinx FPGAs Vivado IDE USB 3.0 10Gb Ethernet I2C RS232 FCC CE Mark MIL-STD-461 DMM Oscilloscope Logic Analyzer Spectrum Analyzer