Senior Compiler Engineer, Smart Network Devices

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$152,000–$241,500 / yr
Posted
114 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $184k
This role $197k
$135k most similar roles pay here $253k

This role pays more than 63% of similar roles. Most pay $151,000–$217,181 — the shaded band above. At the midpoint, this role pays about $197k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Compiler Engineer, Smart Network Devices

As a Senior Compiler Engineer - Smart Network Devices, you will join the Compiler team to advance and develop programmable networks for datacenter scale deployments of Data Processing Units (DPUs). This role bridges the hardware and software boundary, focusing on offloading and accelerating networking, storage, compute, and security services. You will be responsible for implementing static and runtime optimizations, developing proof-of-concept implementations of networking applications, and building advanced compilers. The position requires expertise in compiler technology, performance analysis, code generation, and network protocols. You will utilize C, C++, and Python to perform debugging, test design, and performance analysis. Ideal candidates possess knowledge of the Linux networking stack, hardware packet processing pipelines, and experience with open source compiler code bases to solve complex problems involving resource allocation and programmable infrastructure.

What you'll do

  • Lead the advancement and development of programmable networks for datacenter-scale DPU deployments.
  • Implement static and runtime optimizations using deep knowledge of compiler technologies and resource allocation.
  • Develop proof-of-concept implementations for networking applications to be integrated into company products.
  • Build advanced compilers and optimizations by integrating diverse ideas and technical approaches.
  • Bridge the hardware and software boundary to advocate for and implement programmable technologies.
  • Perform performance analysis, code generation, and debugging using C++, Python, and other relevant tools.
  • Stay current on advancements in compiler technology, networking protocols, and hardware design.

What we're looking for

  • BS/MS in Computer Science or Computer Engineering is required, with a PhD strongly preferred.
  • 5+ years of relevant work or research experience in performance analysis, compiler optimizations, and code generation.
  • Knowledge of compiler technology, optimization techniques, and hardware design.
  • Knowledge of network programming, networking protocols, and layers.
  • Excellent C/C++ and Python programming skills are required.
  • Proficiency in software design including debugging, performance analysis, and test design.
  • Experience with open source compiler code bases and the Linux networking stack is preferred.
  • Proven ability to design or architect compiler frameworks.

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