Senior DL Compiler Engineer, CUDA Tile LPU

Nvidia

Confirmed live today High trust

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CAAustin, TXORWACARedmond, WA
Salary: $152,000–$241,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $212k

This role $197k

$140k $265k

below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $187,250–$235,750 — the blue band above. At the midpoint, this role pays about $197k versus about $212k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1472 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1109 roles with salary data.

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At a glance

TL;DR · Senior DL Compiler Engineer, CUDA Tile LPU

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The Senior DL Compiler Engineer - CUDA Tile LPU will join the CUDA Tile team to support a new tile-based programming model for NVIDIA LPUs. The engineer will design and implement compiler transformations, develop MLIR-based dialects and lowering passes, and optimize the performance of tile-based kernels across multiple generations of NVIDIA GPU and LPU architectures. Key responsibilities include defining public APIs, crafting optimization techniques, and performing general software engineering tasks. Candidates must possess skills in C/C++ programming, compiler optimization, performance analysis, and IR design. Preferred technical knowledge includes MLIR, LLVM, XLA, TVM, CUDA, and OpenCL. This role addresses the technical challenge of ensuring efficient execution of tile-based kernels within the deep learning ecosystem for generative AI and large language models.

Skills

CUDA C++ MLIR LLVM XLA TVM OpenCL Compiler Optimization GPU Architecture Deep Learning IR Design Performance Analysis Software Design Debugging

What you'll do

Design and implement compiler transformations for the CUDA Tile programming model.
Develop MLIR-based dialects and lowering passes for NVIDIA LPUs.
Optimize the performance of tile-based kernels across multiple GPU and LPU architectures.
Define and implement public APIs for the CUDA Tile framework.
Craft and implement advanced compiler and optimization techniques.
Perform performance analysis and debugging for high-performance software.
Lead independent development efforts and define project goals and scope.

What we're looking for

Bachelor's, Master's, or Ph.D. in Computer Science, Computer Engineering, or a related field (or equivalent experience).
3+ years of relevant work or research experience in compiler optimization, performance analysis, and IR design.
Excellent C/C++ programming and software design skills, including debugging, performance analysis, and test design.
Ability to work independently, define project goals and scope, and lead your own development effort.
Strong interpersonal skills and the ability to work in a dynamic product-oriented team.
Knowledge of CPU and/or GPU architecture (preferred).
CUDA or OpenCL programming experience (preferred).
Experience with MLIR, LLVM, XLA, TVM, and deep learning models and algorithms (preferred).

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