Senior AI Performance Architect

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CAAustin, TXFolsom, CARaleigh, NCSanta Clara, CA
Salary
$126,700–$190,100 / yr
Posted
7 days ago
Freshness
Confirmed live today
Closes
Apr 26, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $158k
$111k $269k
below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $173,968–$235,750 — the blue band above. At the midpoint, this role pays about $158k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 580 open roles on FindRole.

Listed pay typically runs $147,900–$218,400 across 557 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Senior AI Performance Architect

The Senior AI Performance Architect joins the Machine Learning Engineering team to drive functional, performance, and power enhancements into hardware for state-of-the-art AI training. This role involves architecting flexible computational blocks supporting various datatypes and precisions, designing memory subsystems for capacity and bandwidth, and developing scale-out architectures including switches and NoCs. You will perform competitive analysis, define performance models, and conduct pre-silicon predictions for ML training workloads. Key requirements include expertise in GPU architectures, LLM hardware requirements, and experience with distributed training frameworks like DeepSpeed or FSDP. The role utilizes C++, Python, and front-end frameworks like PyTorch or TensorFlow. You will solve technical challenges in scaling AI inference and training systems across large numbers of accelerators, servers, and racks for diverse end devices.

What you'll do

  • Architect hardware enhancements to enable efficient training of large-scale AI models.
  • Design flexible computational blocks supporting various datatypes, precisions, and GEMM/GEMV operations.
  • Architect memory subsystems and technologies optimized for capacity, bandwidth, and compute-in-memory requirements.
  • Design scale-out and scale-up architectures including switches, NoCs, and communication collectives.
  • Define performance models and conduct pre-silicon predictions for various ML training workloads.
  • Perform analysis of performance, area, and power trade-offs for future hardware and software algorithms.
  • Codesign hardware with software and GenAI requirements to ensure optimal power efficiency.
  • Conduct competitive analysis of current accelerator and GPU architectures.

What we're looking for

  • Master's degree in Computer Science, Engineering, Information Systems, or related field and 1+ year of relevant work experience.
  • Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 2+ years of relevant work experience.
  • PhD in Computer Science, Engineering, Information Systems, or related field.
  • 3+ years of Hardware Engineering experience defining architecture of GPUs or accelerators used for training AI models.
  • In-depth knowledge of nVidia/AMD GPU capabilities and architectures.
  • Knowledge of LLM architectures and their hardware requirements.
  • Ability to code in C++ and Python.
  • Knowledge of computer architecture, digital circuits, hardware simulators, and communication protocols (preferred).

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