Principal Server Power Management Architect

Qualcomm

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $233,000–$349,600 / yr
Posted: 3 days ago
Closes: Dec 12, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $187k

This role $291k

$103k most similar roles pay here $376k

This role pays more than 93% of similar roles. Most pay $139,200–$235,000 — the shaded band above. At the midpoint, this role pays about $291k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 757 open roles on FindRole.

Listed pay typically runs $151,900–$229,800 across 444 roles with salary data.

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At a glance

TL;DR · Principal Server Power Management Architect

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The Server Power Management Architect role at Qualcomm Technologies is a senior position within the chip design team, focusing on optimizing power efficiency in high-performance server SoCs. The ideal candidate will work closely with CPU and SoC architects to define end-to-end power management strategies that enhance overall system performance while minimizing thermal constraints. Key responsibilities include collaborating across hardware, software, and firmware teams to develop optimal power architectures, executing detailed system-level power modeling, and driving the integration of power delivery systems. Candidates should have extensive experience in designing power-efficient server chips, familiarity with advanced process nodes, and expertise in managing active and idle power states. Proficiency in technologies such as multi-phase buck converters and LDOs is essential, along with a strong understanding of silicon test methodologies for thermal optimization. This role requires deep knowledge of data center SoC architecture and experience in developing solutions for hyperscale environments.

Skills

CPU SoC Power Management Microarchitecture TDP Capping PMICs System Level Power Modeling Thermal Design Voltage Droop Management Current Measurement Telemetry Development Silicon Test Methodologies Hyperscale Data Center Solutions High Performance Design Techniques

What you'll do

Define end-to-end power management architecture for Server SoCs.
Develop optimal power management strategies by collaborating with HW and SW architects.
Execute system-level power modeling to analyze trade-offs in server use cases.
Drive convergence of SoC and board power grid definitions.
Architect detailed power rail sequencing at the SoC and system levels.

What we're looking for

Over 10 years of experience in power management for CPU and SoCs.
At least 5 years of experience with high-performance server chips.
Strong expertise in managing active power, idle low power, and silicon/system limits.
Experience in designing multi-phase buck converters and LDOs for power delivery systems.
Bachelor's degree in Computer Science/Engineering, Electrical Engineering, or related field.
Collaborative skills to work with HW, SW, and FW architects on optimal power management.

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