Principal Memory Controller Architect | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
US
Salary
$165,600–$296,400 / yr
Posted
1 day ago
Closes
Dec 1, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $216k
This role $231k
$124k most similar roles pay here $315k

This role pays more than 74% of similar roles. Most pay $196,692–$235,000 — the shaded band above. At the midpoint, this role pays about $231k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · Principal Memory Controller Architect | Microsoft Careers

As the Principal Memory Controller Architect at Cobalt CPUs, you will join a dynamic team focused on developing cutting-edge custom silicon solutions for Microsoft’s cloud infrastructure. Your primary responsibilities include architecting and developing memory controllers to support advanced DDR technologies such as DDR5, LPDDR, and HBM, while collaborating with micro-architects, verification teams, and vendors to drive features into production. You will also work closely with the performance modeling team to optimize system-on-chip (SoC) designs for Azure workloads, ensuring high performance and efficiency across Microsoft’s cloud hardware ecosystem. This role requires expertise in memory technology roadmaps, SoC memory hierarchy, and emerging memory technologies, along with a strong background in electrical engineering or computer science, typically at the doctoral level with extensive industry experience.

What you'll do

  • Architect and develop custom memory controllers supporting advanced DDR technologies.
  • Review memory technology roadmaps to integrate upcoming standards like DDR5, DDR6, LPDDR, HBM.
  • Collaborate with micro-architects, verification teams to drive new features into production.
  • Evaluate vendor IPs and recommend solutions for memory controller designs.
  • Work with performance modeling team to analyze SOC/platform Azure workload results.
  • Identify full stack optimization opportunities within the context of the overall memory hierarchy.

What we're looking for

  • Doctorate or Master's degree in relevant field with extensive technical engineering experience.
  • 1+ year(s) experience leading projects from beginning-to-end.
  • Delivered architecture/design/verification specs for multiple generations of Memory Controllers.
  • Familiarity with DDR JEDEC specifications and emerging memory technologies.
  • Experience in SoC memory hierarchy/architecture.

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