Principal Engineer, CPU Architecture & Performance Research

Samsung Semiconductor

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$219,000–$351,000 / yr
Posted
today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $216k
This role $285k
$146k most similar roles pay here $373k

This role pays more than 88% of similar roles. Most pay $180,362–$251,000 — the shaded band above. At the midpoint, this role pays about $285k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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At a glance

TL;DR · Principal Engineer, CPU Architecture & Performance Research

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The Principal CPU Architecture & Performance Engineer role at the Architecture Research Lab involves leading the definition, analysis, and optimization of next-generation RISC-V microarchitectures. This senior position focuses on end-to-end performance across architectural trade-offs, workload characterization, simulation, and silicon bring-up correlation. The engineer will collaborate with architecture, design, compiler, and system teams to drive performance and efficiency for various real-world workloads. Key responsibilities include defining CPU micro-architectural features, leading performance analysis using simulators, developing and validating performance models, identifying bottlenecks, and driving alignment between architecture and implementation. Preferred candidates have extensive experience in CPU microarchitecture, RISC-V or similar architectures, and strong programming skills in C/C++ and Python, along with hands-on experience with architectural simulators like gem5.

Skills

RISC-V C/C++ Python gem5 ARM X86 Out-of-order execution Branch prediction Pipelines Speculation Cache coherence Memory systems Prefetching NUMA effects SIMD Vectors VME Compiler optimizations Hardware/software co-design Performance modeling RTL Architectural simulators Cycle-accurate simulation Trace-driven analysis Statistical modeling

What you'll do

  • Define and evaluate CPU microarchitectural features for future RISC-V cores.
  • Lead performance analysis using simulators and RTL for next-gen CPUs.
  • Develop and validate cycle-accurate, trace-driven, and statistical performance models.
  • Characterize workloads to translate findings into architectural requirements.
  • Identify performance bottlenecks and propose data-driven optimizations.

What we're looking for

  • Master’s degree with 18+ years or PhD with 15+ years in Computer Engineering, Science.
  • Extensive experience (10+) in CPU microarchitecture and performance engineering.
  • Proficiency in RISC-V, ARM, or X86 architectures; out-of-order execution expertise.
  • Hands-on use of architectural simulators like gem5 and strong C/C++/Python programming skills.
  • Expertise in cache coherence, memory systems, prefetching, NUMA effects, and compiler optimizations.
  • Ability to analyze large performance datasets, identify bottlenecks, and propose data-driven optimizations.

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