Principal Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose Innovation Drive, CA
Salary: $141,300–$226,000 / yr
Posted: 48 days ago
Closes: Oct 24, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $184k

$130k most similar roles pay here $246k

This role pays less than 54% of similar roles. Most pay $161,500–$232,000 — the shaded band above. At the midpoint, this role pays about $184k versus about $197k for comparable roles.

Based on 237 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 96 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 94 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Principal Engineer

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Broadcom's Core Switching Group is hiring a Logic Design Engineer to join their team of innovators focused on high-performance Ethernet switch chip development for hyperscale data centers and cloud providers. In this role, you will work closely with architects and verification engineers to design and implement efficient RTL code for complex networking ASICs, participating in all stages from micro-architecture specification through unit verification and timing convergence. The ideal candidate should have a strong background in digital design, particularly Verilog-based RTL development, and experience with Ethernet and other networking protocols. Familiarity with packet processing architectures, low power design techniques, and scripting languages like Python or Perl is preferred. This position offers the opportunity to contribute to cutting-edge technologies that enable massive network bandwidth for AI infrastructure and cloud applications.

Skills

Verilog RTL Ethernet TCP/IP MPLS Python Perl ASIC deep submicron technologies timing closure low power design clock domain crossing

What you'll do

Develop micro-architecture specifications for complex networking ASICs.
Implement efficient RTL designs using Verilog for high-performance Ethernet switches.
Conduct unit verification to ensure the correctness of implemented components.
Analyze timing issues and implement ECOs to achieve timing closure on ASICs.
Debug hardware issues through detailed analysis and reviews.

What we're looking for

B.S. in Electrical/Computer Engineering or related field with 8+ years of experience.
M.S. in Electrical/Computer Engineering or related field with 6+ years of experience.
4+ years of Verilog-based RTL design and verification experience in deep submicron technologies.
Familiarity with Ethernet, TCP/IP, MPLS, tunneling, and other networking protocols.
Experience achieving timing closure on high-performance ASICs.

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