Senior Photonic Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$139,400–$209,200 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Closes
Feb 23, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $168k
This role $174k
$127k most similar roles pay here $218k

This role pays more than 55% of similar roles. Most pay $142,400–$193,000 — the shaded band above. At the midpoint, this role pays about $174k versus about $168k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Photonic Engineer

Photonic Engineer, Senior joins the RFIC Design team to develop photonic integrated circuits for next-generation silicon photonics platforms targeting high-speed optical interconnect and DWDM transceiver applications. The role involves designing active and passive components from specification through tape-out using 3D structure simulation tools and foundry PDKs. Key responsibilities include performing FDTD, MODE, INTERCONNECT, and CHARGE simulations, developing script-based workflows with AI to automate layout generation and data analysis, and collaborating cross-functionally with systems teams to validate electro-optical performance. The candidate will utilize Lumerical, Python, and layout editors like Cadence Virtuoso or KLayout to solve complex problems in optical link budgets and wavelength control loops. This position focuses on the technical challenge of closing the loop between simulation and hardware through post-fabrication characterization to ensure high-performance transceiver reliability.

What you'll do

  • Design active and passive photonic components from specification through tape-out using 3D simulation tools and foundry PDKs.
  • Perform 3D photonic simulations to validate device performance and iterate designs toward target specifications.
  • Develop and maintain script-based workflows using AI tools to automate parameter sweeps, layout generation, and data analysis.
  • Review and sign off on physical layouts produced by the dedicated layout engineering team.
  • Conduct co-simulations with EIC and packaging teams to validate electro-optical performance in DWDM transceiver systems.
  • Execute post-fabrication characterization tests to correlate hardware data with simulation models.
  • Maintain technical documentation including design specifications, simulation methodologies, and tape-out checklists.

What we're looking for

  • Bachelor's degree in EE, Physics, or Optics with 5+ years of PIC design experience, OR Master's with 3+ years, OR PhD with 1+ year.
  • 2+ years of hands-on experience with Lumerical (FDTD, MODE, CHARGE, INTERCONNECT), Python, and layout editors like Cadence Virtuoso or KLayout.
  • Experience designing active and passive photonic components using silicon-photonics foundry PDKs.
  • System-level understanding of optical link budgets, DWDM channel plans, OMA/TDECQ, and transceiver power allocation.
  • Preferred experience in Co-Packaged Optics (CPO) design and PIC-EIC co-design for high-speed transceivers.
  • Proficiency with system-level photonic simulation tools such as VPI Photonics or Lumerical Zemax OpticStudio.
  • Experience with DWDM wavelength control loops, thermal tuning, and closed-loop resonance lock for ring-modulator transmitters.
  • Track record of photonic tape-outs with post-silicon characterization and publication or patent filings in integrated photonics.

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