Graphics FE Integration Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
—
Salary
$150,400–$277,600 / yr
Posted
15 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 70% of similar roles. Most pay $162,000–$231,150 — the shaded band above. At the midpoint, this role pays about $214k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Graphics FE Integration Engineer

As a Graphics FE Integration Engineer within the Silicon Technologies group, you will join the GPU FE Design integration team to develop high-performance, power-efficient GPU technology. Your daily responsibilities include creating GPU RTL by integrating various IPs while adhering to architectural parameters, physical constraints, DFT logic, and power intent. You will perform RTL integration, partitioning, design analysis, qualification, packaging, and delivery, while running logic equivalence checking between designs. To ensure implementation readiness, you will utilize RTL linting, custom checks, and unit level synthesis. The role requires proficiency in Verilog, System Verilog, and scripting languages like Perl, Ruby, or Python. You will also apply knowledge of PPA optimization, codeline management, and logic design principles to solve complex problems across multiple technical domains while collaborating with architecture, IP, DV, SOC, DFT, and IMPL teams.

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Graphics FE Integration Engineer

Apple Inc

Austin, TX 15 days ago
Verilog System Verilog Python Perl Ruby RTL DFT LEC Lint Synthesis PPA Optimization Invio Genus SIMD Architecture Logic Design
3+ yrs exp