Front End Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
5 days ago
Closes
Dec 20, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $144k
$103k most similar roles pay here $231k

This role pays less than 83% of similar roles. Most pay $159,850–$213,375 — the shaded band above. At the midpoint, this role pays about $144k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 828 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 508 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Front End Design Engineer

Join the RTL design and verification team at Qualcomm Technologies as a mid-level engineer responsible for designing and verifying digital IPs used across various Qualcomm chips. You will work on critical high-speed clock IPs, power-sequencing blocks, custom FIFOs, and high-speed latch arrays, collaborating closely with SOC design and verification teams to integrate and support front-end deliverables. Essential skills include experience in RTL design or verification, knowledge of OOP concepts, proficiency in System Verilog, UVM/OVM, and Python scripting for automation. Familiarity with power-aware verification, synthesis, STA, and ASIC backend integration tools is beneficial. This role requires a strong background in digital logic design, simulation methodologies, and formal verification techniques to ensure robust IP delivery.

What you'll do

  • Develop RTL design for digital IPs used in Qualcomm chips.
  • Verify and test digital IPs using simulation and formal verification methodologies.
  • Collaborate on specification and integration of front-end deliverables for Soft/Hard-Macros.
  • Work closely with SOC design teams to support IP development and delivery.
  • Implement low power design techniques and understand power-aware verification concepts.

What we're looking for

  • 2+ years of professional experience in RTL design or verification of digital IPs.
  • Strong knowledge in digital logic design including data path and FSM design.
  • Proficiency in Verilog, System Verilog, Perl, and circuit design.
  • Experience with OOP concepts and HVL such as System Verilog, UVM/OVM & System C.
  • Ability to use simulation and formal verification methodologies for test plans.
  • Good understanding of synthesis and STA, with knowledge of low power design techniques.

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