FPGA Firmware & Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $164,000–$246,000 / yr
Posted: 4 days ago
Closes: Dec 23, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $205k

$134k most similar roles pay here $258k

This role pays more than 65% of similar roles. Most pay $160,000–$216,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 528 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 507 roles with salary data.

Most-posted roles

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At a glance

TL;DR · FPGA Firmware & Design Engineer

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As a Principal ASIC Design Engineer at Qualcomm Technologies, you will join the cutting-edge semiconductor design team to develop advanced architectures and circuit specifications for complex system-on-chip (SoC) projects. Your daily responsibilities include creating detailed logic designs, evaluating process flows from high-level design through verification, and utilizing tools like RTL to GDS Flow and Virtuoso to enable highly sophisticated architecture and design of multiple blocks. You will also write comprehensive technical documentation and mentor junior engineers in the team. The role requires extensive experience with ASIC design, verification methods, scripting languages, and interaction with senior leadership. Ideal candidates possess a strong background in EDA/IP/ASIC projects and are proficient in tools such as Cadence Virtuoso for custom circuit design/layout flow.

Skills

Virtuoso RTL to GDS Flow Python Perl TCL SystemVerilog UVM DVFlow CI/CD Git Linux Windows

What you'll do

Creates advanced architectures and circuit specifications based on system-level requirements.
Evaluates complex process flows from high-level design to verification stages.
Utilizes specialized tools for executing highly advanced architecture and design of multiple complex blocks/SoC.
Writes detailed technical documentation for EDA/IP/ASIC projects.
Reviews technical documentation for junior engineers.

What we're looking for

9+ years of ASIC design or related work experience.
3+ years of experience with architecture and design tools and scripting languages.
3+ years of experience in design verification methods.
2+ years of interaction with senior leadership roles (Director level and above).
Strong proficiency in utilizing EDA/IP/ASIC project documentation and technical writing.

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