FE RTL Infrastructure CAD Engineer

What you'll do

• Develop and support infrastructure for design and verification teams to modify, analyze, and verify RTL.
• Manage RTL gatekeeping infrastructure for design collateral and soft IP development/release methodologies.
• Administer Perforce systems to ensure the integrity and performance of the version control ecosystem.
• Maintain a centralized configuration management system for loading different design views into front-end flows.
• Build generative AI solutions to accelerate engineering productivity and improve infrastructure reliability.
• Manage internal training materials and coordinate vendor training sessions for designer and verification engineers.
• Create, monitor, and maintain high-quality infrastructure and flows for Apple Silicon chip production.

What we're looking for

• Minimum of a BS degree and 3 years of relevant experience.
• Expertise in programming in Python or Perl.
• Knowledge in Verilog and SystemVerilog.
• Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing, or Lint (preferred).
• Understanding of Front-End RTL Build or Construction flows (preferred).
• Excellent communication, debug, and root causing skills (preferred).
• Customer-oriented mindset and support experience (preferred).
• Experience in contributing to large-scale software system development from specification to deployment (preferred); MSEE/CE/CS degree preferred.