ESD and Latch-up Test Engineer

Nvidia

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
120 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $167k
This role $177k
$118k most similar roles pay here $229k

This role pays more than 62% of similar roles. Most pay $130,500–$204,200 — the shaded band above. At the midpoint, this role pays about $177k versus about $167k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1404 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1052 roles with salary data.

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At a glance

TL;DR · ESD and Latch-up Test Engineer

As an ESD and Latch-up Test Engineer, you will join a team focused on advanced semiconductor technologies to perform qualification tests for GPU and Tegra products. Your daily responsibilities include planning and performing ESD and latch-up qualifications, developing HBM, CDM, Latch Up I-test, and overvoltage stress programs according to JEDEC and AEC standards. You will collaborate with external vendors to build and validate test fixtures while conducting characterization on test chips featuring new I/O interfaces and protection structures. The role requires technical expertise in CMOS I/O circuits, experience with MK4 and Orion testers, and proficiency in analyzing IC electrical test data. You will also debug failing pins, maintain in-house equipment like TLP and 2-pin testers, and manage internal databases to ensure reliability for high-performance computing components.

What you'll do

  • Plan and perform ESD and latch-up qualification for new and updated GPU and Tegra products.
  • Develop HBM, CDM, Latch Up I-test, and overvoltage stress programs according to JEDEC/AEC standards.
  • Collaborate with external vendors to build and validate test fixtures including boards, sockets, and thermal plungers.
  • Conduct ESD and latch-up characterization on test chips featuring new I/O interfaces and protection structures.
  • Debug marginal or failing pins and work with Failure Analysis teams to identify root causes.
  • Maintain, troubleshoot, and calibrate in-house test equipment such as HBM, latch-up, and TLP testers.
  • Update and maintain internal ESD and latch-up databases, documentation, and online resources.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Physics, or equivalent experience.
  • 5+ years of related experience.
  • Familiarity with JEDEC and AEC standards related to ESD and latch-up qualification.
  • Practical experience working with MK4 and Orion testers during the development of ESD and Latch-up stress programs.
  • Solid knowledge of CMOS I/O circuits and ESD protection structures.
  • Proficiency in analyzing IC electrical test data and interpreting qualification results.
  • Experience debugging ESD or latch-up failures at the pin, circuit, or product level.
  • Some experience with 93K tester program development (preferred).

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