Director of eSoftware Engineering, FPGA, Equities Low Latency Trading

JPMorgan Chase

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Jersey City, NJ
Posted
81 days ago
Freshness
Confirmed live yesterday

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Similar $203k
$152k most similar roles pay here $245k

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About JPMorgan Chase

JPMorgan Chase & Co. is a global financial services firm and one of the largest banks in the world, offering investment banking, commercial banking, asset management, and consumer financial services.

JPMorgan Chase currently has 1117 open roles on FindRole.

Listed pay typically runs $186,160–$215,000 across 7 roles with salary data.

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TL;DR · Director of eSoftware Engineering, FPGA, Equities Low Latency Trading

Director of eSoftware Engineering - FPGA / Equities Low Latency Trading joins the Equities Electronic Trading team to provide technical leadership in designing and delivering ultra-low latency market infrastructure. The role involves architecting FPGA-based pipelines for market data ingest, processing, distribution, and trading workflows while ensuring production-grade operational controls. Key responsibilities include developing high-performance network subsystems, integrating Layer 1 switching, and managing microwave connectivity solutions. The candidate will drive the adoption of AI-assisted and spec-driven FPGA development and verification workflows to improve quality and time-to-market. Required technical skills include deep expertise in TCP/IP, UDP, multicast, ARP, PTP, and Python with Cocotb for verification; familiarity with SystemVerilog and UVM is also valued. The role addresses the critical challenge of building deterministic, high-performance systems within the complex domain of equities electronic trading and high-frequency trading environments.

What you'll do

  • Architect and optimize ultra-low latency FPGA pipelines for market data processing and trading workflows.
  • Design high-performance network subsystems on FPGA including TCP/IP, UDP, multicast, and PTP time synchronization.
  • Integrate Layer 1 switching and low-latency signal distribution across physical and topology constraints.
  • Manage the end-to-end program lifecycle from initial requirements through production rollout while coordinating with internal teams and vendors.
  • Develop robust verification strategies using Python and Cocotb to ensure high functional coverage and fast debug cycles.
  • Drive timing closure, floorplanning, and performance predictability under realistic traffic conditions.
  • Lead the adoption of AI-assisted and spec-driven workflows for FPGA development, including automated RTL generation and review.

What we're looking for

  • Formal training or certification in software engineering concepts.
  • 10+ years of applied experience in software engineering.
  • 5+ years of experience leading technologists to manage and solve complex technical items.
  • Hands-on FPGA development experience in low-latency electronic trading and HFT systems.
  • Advanced verification capability using Python and Cocotb, with familiarity in SystemVerilog and UVM.
  • Deep networking expertise including TCP/IP, UDP, IP, multicast, ARP, and PTP.
  • Experience with Layer 1 switching and ultra-low latency signal distribution.
  • Hands-on experience with microwave or wireless low-latency connectivity for market access.

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