Director of eSoftware Engineering, FPGA / Equities Low Latency Trading

JPMorgan Chase

Quick summary

Work type
On-site
Location
Jersey City, NJ
Salary
$204,250–$285,000 / yr
Posted
4 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $245k
$137k most similar roles pay here $301k

This role pays more than 89% of similar roles. Most pay $177,250–$220,825 — the shaded band above. At the midpoint, this role pays about $245k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About JPMorgan Chase

JPMorgan Chase & Co. is a global financial services firm and one of the largest banks in the world, offering investment banking, commercial banking, asset management, and consumer financial services.

JPMorgan Chase currently has 436 open roles on FindRole.

Listed pay typically runs $152,000–$215,000 across 230 roles with salary data.

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View all roles at JPMorgan Chase

At a glance

TL;DR · Director of eSoftware Engineering, FPGA / Equities Low Latency Trading

Role Posting Log in to save

As a Director of eSoftware Engineering in FPGA development for equities low-latency trading at JPMorgan Chase, you will lead a technical team to design and deliver ultra-low latency market infrastructure. Your responsibilities include architecting and optimizing FPGA-based pipelines for market data processing and distribution, as well as developing high-performance network subsystems with deep TCP/IP expertise. You will also manage Layer 1 switching and low-latency signal distribution, collaborate with external vendors on connectivity solutions, and own the verification strategy using Python and Cocotb. Additionally, you will guide the team in adopting AI-assisted FPGA development workflows and ensure robust testbenches for high functional coverage. This role requires extensive experience in FPGA development for HFT systems, advanced networking knowledge, and proficiency in tools like SystemVerilog and UVM.

Skills

FPGA Python Cocotb SystemVerilog UVM TCP UDP IP multicast ARP PTP Layer 1 switching microwave/wireless connectivity PCIe DMA AXI high-speed transceivers high-speed Ethernet MAC/PCS

What you'll do

  • Architect and implement ultra-low latency FPGA-based pipelines for market data.
  • Design high-performance network subsystems on FPGA with deep TCP/IP expertise.
  • Engineer Layer 1 switching and low-latency signal distribution capabilities.
  • Own verification strategy, building robust testbenches in Python/Cocotb.
  • Drive timing closure and performance predictability across realistic traffic conditions.
  • Lead a team of hardware and software engineers through program lifecycle.
  • Scale AI-assisted and spec-driven workflows for FPGA development and verification.

What we're looking for

  • Extensive experience leading FPGA development in low-latency electronic trading systems.
  • Proven ability to design and implement ultra-low latency FPGA pipelines with end-to-end performance measurement.
  • Expertise in advanced verification using Python, Cocotb, SystemVerilog, and UVM for robust testbenches.
  • Deep understanding of networking protocols including TCP/IP, UDP, multicast, ARP, and PTP.
  • Hands-on experience with Layer 1 switching and ultra-low latency signal distribution concepts.
  • Experience with microwave/wireless low-latency connectivity solutions for market access environments.
  • Strong technical leadership skills to guide teams through architecture, design reviews, and execution.

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