Director of Engineering for ML hardware design & Architecture

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$228,400–$342,600 / yr
Posted
24 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $237k
This role $286k
$165k $362k
below market most similar roles pay here above market

This role pays more than 82% of similar roles. Most pay $208,743–$265,125 — the blue band above. At the midpoint, this role pays about $286k versus about $237k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 558 open roles on FindRole.

Listed pay typically runs $152,130–$222,500 across 534 roles with salary data.

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At a glance

TL;DR · Director of Engineering for ML hardware design & Architecture

The Director of Engineering for ML hardware design & Architecture joins the Machine Learning Hardware Accelerator team to drive the definition and analysis of next-generation ML hardware accelerator architectures. This role focuses on vision applications for mobile and emerging products, specifically targeting computer vision workloads like image classification, object detection, and video analytics. The successful candidate will architect high-performance, power-efficient designs, optimize performance, power, and area tradeoffs, and define micro-architectures for ML algorithms. Key responsibilities include leading hardware IP development and collaborating with global software and systems teams. Required expertise includes CPUs, GPUs, DSPs, memory, and bandwidth analysis. Candidates must utilize tools such as Verilog, SystemVerilog, HLS, C/C++, and SystemC, while applying knowledge of ML frameworks like TensorFlow Lite and ONNX to solve complex hardware problems.

What you'll do

  • Architect high-performance, power-efficient ML hardware accelerator designs for computer vision workloads.
  • Analyze and optimize hardware designs for performance, power, and area (PPA) tradeoffs.
  • Define hardware micro-architecture for the efficient implementation of ML algorithms.
  • Lead HW IP development by coordinating with RTL design, verification, synthesis, and physical design teams.
  • Use models, simulators, profilers, and real hardware to quantitatively justify architectural decisions.
  • Apply knowledge of CPUs, GPUs, DSPs, memory, and bandwidth analysis to ML hardware design.
  • Invent and file patents for innovative hardware solutions.

What we're looking for

  • Master's degree in Computer or Electrical Engineering, Computer Science, or related field and 15+ years of industry experience.
  • Experience in hardware development for ML, multimedia, or accelerator technologies like vision, imaging, video, or audio.
  • Experience in system or chipset development for SoC products, preferably in the mobile market.
  • Experience with SoC bus, interconnect, and memory technologies.
  • Experience with ML frameworks and accelerator standards such as TensorFlow Lite or ONNX.
  • Proficiency in VLSI design and verification using Verilog, SystemVerilog, or HLS.
  • Proficiency in C, C++, and SystemC programming.
  • Deep domain knowledge in ML for vision and experience collaborating with global teams (preferred).

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