Design Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
1 day ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $175,400–$236,300 — the shaded band above. At the midpoint, this role pays about $255k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3518 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2727 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the wireless silicon development team to support the design of wireless SoCs with a focus on energy-efficient designs and new technologies. This role involves collaborating with architecture and RTL power designers to define power vector tests and verify functionality correctness. Key responsibilities include developing test plans and environments in C or UVM, creating complex power vector tests for wireless protocol designs in C or assembly, and performing cross-functional reviews. The candidate must possess skills in C/C++, assembly, Verilog, and SystemVerilog, with a solid understanding of digital logic design, chip architecture, and microarchitecture. The work involves solving technical problems through constrained random testing, debugging, and utilizing reusable verification frameworks to ensure functional products are delivered to customers.

What does a Design Verification Engineer earn in California?

Median $199724 from 60 postings across 7 companies.

See salary data

Skills

UVM SystemVerilog Verilog C C++ Assembly Python Makefile Constrained Random Testing Emulation Digital Logic Design Chip Architecture Microarchitecture Wireless Protocols Power Analysis

What you'll do

  • Define power vector tests and verify functionality correctness for Wireless SoC designs.
  • Develop comprehensive test plans and test environments using C or UVM.
  • Create complex power vector tests for wireless protocol designs in C or assembly.
  • Execute test plans and perform technical reviews with cross-functional teams.
  • Port simulation tests to emulation environments.
  • Debug complex hardware issues using constrained random testing and reusable verification frameworks.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Experience with C/C++/assembly programming and Verilog/SystemVerilog.
  • Understanding of C compilation flow and makefile.
  • Solid verification skills in problem solving, constrained random testing, and debugging.
  • Solid understanding of reusable verification frameworks.
  • Knowledge of digital logic design, chip architecture, and microarchitecture.
  • Experience in setting UVM/System TB with embedded C tests (preferred).

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