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Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA · Santa Clara, CA
Posted: 31 days ago
Closes: Nov 2, 2026
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $180k

$123k most similar roles pay here $247k

This listing doesn't post a salary. Most similar roles pay $152,037–$208,800.

Based on 238 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 558 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 401 roles with salary data.

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At a glance

TL;DR · Careers

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The Infrastructure IP Team at Qualcomm Technologies seeks a senior-level systems engineer to define and design next-generation SOC infrastructure hardware components such as interconnects, system caches, memory controllers, and system MMUs for ARM architecture-enabled SoCs. This role involves deep understanding of HW architecture, SW interfaces, and the end-to-end silicon design flow, requiring expertise in multi-die architectures, industry-standard protocols like PCIe and CXL, and SOC infrastructure IP. The ideal candidate will have hands-on experience with RTL design, performance modeling, and validation, as well as strong knowledge in quality of service, power management, security, and debug architectures. Excellent communication skills are essential for collaborating across disciplines to drive innovative technologies at scale.

Skills

ARM PCIe CXL USB UFS MIPI UCie RAS MPAM Memory Tagging RTL design Performance modeling Validation SOC architecture NOC SMMU Cache Interrupt Handler Security Power management Quality of Service Clocks Debug architectures Firmware Data Science MLOps

What you'll do

Define HW architecture for next generation SOC infrastructure IPs.
Design multi-die/chiplet architectures with Die-to-Die and Chip-to-Chip Links.
Develop Quality of Service, Clocks, Power management, Security, and Debug features.
Create SW-friendly interfaces for firmware and APIs in HW-SW integration.
Perform performance modeling and validation throughout the design flow.

What we're looking for

Strong knowledge and hands-on experience with multi-die/chiplet architectures and interconnect protocols.
Deep understanding of SOC infrastructure IP (NOC, SMMU, caches) and their software interfaces.
Experience in performance modeling, RTL design, and complete silicon end-to-end design flow.
Excellent communication skills for defining SW-friendly HW architectures.
Strong knowledge in quality of service, power management, security, and debug architectures.

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