CAD Engineer, EMIR Signoff

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $216,200–$324,800 / yr
Posted: 21 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $209k

This role $270k

$129k $346k

below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $177,237–$241,750 — the blue band above. At the midpoint, this role pays about $270k versus about $209k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CAD Engineer, EMIR Signoff

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CAD Engineer – EMIR Signoff joins the Silicon Technologies group to ensure verification and analysis for complex mixed-signal designs prior to tapeout. This role involves developing and refining signoff methodologies at the gate and transistor levels, specifically focusing on power/EMIR analysis. Key responsibilities include performing functional static/dynamic IR analysis, scan-mode IVD analysis, package model handling, power EM analysis, signal EM, power switch modeling, and IP reuse. The engineer will define signoff requirements, partner with Design, CAD, and Technology teams to confirm EDA flows, and provide frontline support for debug requests. Required skills include experience with Redhawk, Voltus, and Totem tools, along with proficiency in Perl and Python. The role also explores AI/ML and LLM-driven techniques to accelerate analysis and automate flow debugging.

Skills

EMIR Analysis Redhawk Voltus Totem Python Perl Mixed-Signal Design CMOS Dynamic IR Analysis Scan-mode IVD Power EM Analysis EDA Flow AI/ML LLM Signoff Methodologies

What you'll do

Perform verification and analysis on complex mixed-signal designs prior to tapeout.
Develop and refine signoff methodologies for power/EMIR analysis at the gate and transistor levels.
Execute functional static/dynamic IR analysis and scan-mode IVD analysis.
Manage package model handling, power EM analysis, signal EM, and power switch modeling.
Implement AI/ML and LLM-driven techniques to automate flow debugging and surface design anomalies.
Define signoff requirements early in the project lifecycle and confirm EDA flow setups.
Provide frontline support to design groups for enablement, enhancement, and debug requests.

What we're looking for

Bachelor of Science degree.
10+ years of relevant industry experience.
Experience in CAD, EMIR analysis, or related circuit design roles (preferred).
Solid understanding of circuit design principles and EMIR analysis at the transistor and gate level (preferred).
In-depth knowledge of industry-leading tools such as Redhawk, Voltus, and Totem (preferred).
Experience in simulation and power analysis to verify circuit performance (preferred).
Strong understanding of CAD flows (preferred).
Proficiency in scripting/programming languages like Perl and Python (preferred).