ASIC Power Design Engineer II

Cisco

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $125,700–$203,100 / yr
Employment: Full-time
Posted: 3 days ago
Freshness: Confirmed live yesterday
Closes: Dec 18, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $164k

$114k $236k

below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $164k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 303 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 218 roles with salary data.

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At a glance

TL;DR · ASIC Power Design Engineer II

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The ASIC Power Design Engineer II joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. In this role, you will implement and optimize low-power design methodologies, including clock gating, power gating, multi-Vt, and dynamic voltage and frequency scaling using UPF/CPF power intent. You will perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower across various operating modes and PVT corners. Key responsibilities include collaborating with RTL design and architecture teams to identify power bottlenecks, achieving timing closure on advanced FinFET and GAA process nodes, and developing automated workflows. Required skills include proficiency in SystemVerilog, Verilog, and scripting with Python, TCL, or Perl. You will also perform post-silicon power validation and correlation against pre-silicon models.

Skills

ASIC Design Power Analysis SystemVerilog Verilog Python TCL Perl Synopsys PrimePower Synopsys Design Compiler Fusion Compiler IC Validator Cadence Innovus Synopsys Prime Time StarRC Siemens Calibre Ansys RedHawk Voltus Linux Unix UPF CPF FinFET GAA

What you'll do

Implement and optimize low-power design methodologies including clock gating, power gating, and DVFS.
Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower.
Identify power bottlenecks and guide RTL and micro-architectural power optimizations with design teams.
Achieve timing closure, signal integrity, and power targets across advanced FinFET and GAA process nodes.
Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
Participate in post-silicon power and performance validation and correlation against pre-silicon models.

What we're looking for

Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience.
Strong familiarity with low-power design concepts and techniques including UPF/IEEE 1801, clock gating, and multi-voltage domains.
Proficiency with hardware description languages such as SystemVerilog and Verilog.
Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
Familiarity with Linux/Unix development environment.
Direct experience running activity-driven power analysis using FSDB/VCD/SAIF waveforms generated from gate-level and RTL simulations (preferred).
Experience with industry-standard EDA tools such as Synopsys Design Compiler, Fusion Compiler, IC Validator, or Cadence Innovus (preferred).
Experience with power integrity, IR-drop, or EM analysis tools such as Ansys RedHawk or Voltus (preferred).