Analog Layout Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $163,300–$290,100 / yr
Posted: 39 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $180k

This role $227k

$118k most similar roles pay here $309k

This role pays more than 89% of similar roles. Most pay $151,500–$208,437 — the shaded band above. At the midpoint, this role pays about $227k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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View all roles at Apple Inc

At a glance

TL;DR · Analog Layout Engineer

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As an Analog Layout Engineer at our cutting-edge semiconductor company, you will join a dynamic and innovative team focused on developing advanced analog circuits for next-generation devices. Your primary responsibilities include creating high-quality layout designs using Cadence Innovus, ensuring compliance with design rules and specifications. You will work closely with circuit designers to optimize layouts for performance, power consumption, and area efficiency. Additionally, you will develop custom PCells and contribute to the automation of layout processes to enhance productivity and accuracy. Ideal candidates possess a strong background in MSEE or Ph.D., along with hands-on experience in CAD Automation and PCell creation. This role demands expertise in analog circuit design, layout techniques, and an understanding of semiconductor fabrication processes.

Skills

Cadence_Innovus CAD_Automation PCell_creation

What you'll do

Design and optimize analog/mixed-signal circuits for semiconductor devices.
Create physical layouts that meet performance, power, and area requirements.
Perform layout verification using DRC/LVS checks to ensure design integrity.
Collaborate on the development of custom PCells for layout automation.
Implement design rules and guidelines in layout creation processes.

What we're looking for

3+ years of professional experience in analog layout design.
Proficient in using Cadence Innovus and other EDA tools.
Experience with CAD automation and scripting languages.
Strong background in creating PCells for custom IC layouts.
MSEE or Ph.D. in Electrical Engineering or related field required.

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