Analog Layout Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $172,100–$305,600 / yr
Posted: 39 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $180k

This role $239k

$116k most similar roles pay here $326k

This role pays more than 91% of similar roles. Most pay $151,500–$208,437 — the shaded band above. At the midpoint, this role pays about $239k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Analog Layout Engineer

Apply Now Log in to save

As an Analog Layout Engineer at our cutting-edge hardware team, you will play a crucial role in the design and development of advanced semiconductor devices. Your primary responsibilities include creating high-quality layout designs for analog circuits using Cadence Innovus, ensuring compliance with stringent design rules and performance specifications. You will work closely with circuit designers to translate schematic diagrams into optimized physical layouts, focusing on minimizing parasitic effects while maximizing yield and reliability. Additionally, you will develop custom PCells and contribute to the automation of layout processes to enhance efficiency and scalability. This role demands expertise in semiconductor fabrication technologies and a deep understanding of analog circuit behavior at the physical level.

Skills

Cadence_Innovus CAD_Automation PCell_creation

What you'll do

Design and optimize analog/mixed-signal circuit layouts for high-performance ICs.
Implement layout techniques to meet performance, power, and area goals.
Perform detailed rule checking and DRC/LVS verification on designs.
Collaborate with design engineers to resolve layout-related issues efficiently.
Create and maintain physical design documentation and libraries.

What we're looking for

5+ years of experience in analog layout design and verification.
Proficient in using Cadence Innovus for physical design implementation.
Experience with CAD automation tools and techniques.
Expertise in creating PCells for custom IC layouts.
MSEE or Ph.D. in Electrical Engineering or related field required.

Save