AI/ML Camera Lead Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$179,000–$268,400 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Jan 30, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $216k
This role $224k
$164k most similar roles pay here $280k

This role pays more than 62% of similar roles. Most pay $184,975–$246,150 — the shaded band above. At the midpoint, this role pays about $224k versus about $216k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 621 open roles on FindRole.

Listed pay typically runs $147,900–$222,500 across 601 roles with salary data.

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At a glance

TL;DR · AI/ML Camera Lead Engineer

The AI/ML Camera Lead Engineer joins the Camera Engineering team to drive innovation in human and computer vision technologies for mobile, automotive, XR, IoT, and compute devices. This technical leadership role involves designing and owning ASIC IP blocks from architecture through RTL delivery while collaborating with architects to define micro-architectures for image and video processing pipelines. The engineer will develop high-quality RTL using Verilog, SystemVerilog, or VHDL, ensuring performance, power, and area goals are met through synthesis and timing analysis. Additionally, the role focuses on GenAI for hardware design, where the candidate will oversee internal benchmark suites for LLMs, develop agentic AI solutions for RTL workflows, and prototype research directions. Required skills include proficiency in Python, C++, or Java, experience with camera/ISP hardware, and practical knowledge of LLMs and embedding models applied to engineering workflows.

What you'll do

  • Define and implement micro-architectures for image and video processing pipelines.
  • Design and own ASIC IP blocks from initial architecture through RTL delivery.
  • Develop high-quality RTL using Verilog, SystemVerilog, or VHDL for camera and multimedia hardware.
  • Perform synthesis to ensure performance, power, and area goals are met.
  • Execute and review CDC, low-power, timing, and design rule checks.
  • Oversee the delivery of internal benchmark suites and agentic AI solutions for hardware design workflows.
  • Identify and prototype GenAI research directions for hardware and chip design.
  • Guide GenAI concepts from R&D into practical internal deployment.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 6+ years of experience with a Bachelor's, 5+ years with a Master's, or 4+ years with a PhD in a relevant engineering field.
  • Strong hands-on experience with ASIC RTL design using Verilog, SystemVerilog, or VHDL.
  • Solid understanding of ASIC design flows including synthesis, timing, CDC, and low-power analysis.
  • Experience with camera/ISP, image processing, video, multimedia, computer vision, or DSP hardware.
  • Proficiency in Python (and/or C++/Java) for tooling, automation, and GenAI evaluation workflows.
  • Practical experience with LLMs, embedding models, or agentic AI systems applied to engineering workflows.
  • Strong communication skills and ability to work effectively in cross-functional teams.

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