AI/ML Camera Lead Engineer

What you'll do

• Design and implement ASIC IP blocks from initial architecture through RTL delivery.
• Develop high-quality RTL using Verilog, SystemVerilog, or VHDL for camera and multimedia hardware.
• Run synthesis and review results to ensure performance, power, and area (PPA) goals are met.
• Perform and review CDC, low-power, timing, and design rule checks.
• Oversee the design and delivery of internal benchmark suites for LLMs used in hardware design.
• Develop agentic AI solutions to assist with RTL development, review, debug, and verification workflows.
• Identify and prototype impactful GenAI research directions for hardware and chip design.
• Create and maintain micro-architecture and design documentation.

What we're looking for

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant work experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience.
• Strong hands-on experience with ASIC RTL design and proficiency in Verilog, SystemVerilog, or VHDL.
• Solid understanding of ASIC design flows, including synthesis, timing, CDC, and low-power analysis.
• Experience with camera/ISP, image processing, video, multimedia, computer vision, or DSP hardware.
• Proficiency in Python (and/or C++/Java) for tooling, automation, and GenAI evaluation workflows.
• Practical experience with LLMs, embedding models, or agentic AI systems applied to engineering workflows.
• Experience with SystemC or hardware modeling (preferred).
• Prior ASIC implementation of camera or image processing IP (preferred).
• Experience defining or maintaining benchmarking and evaluation frameworks for ML/LLM systems (preferred).
• Familiarity with agentic AI frameworks or tools used for code generation, review, or analysis (preferred).
• Scripting experience in Python, TCL, Perl, or shell supporting RTL or GenAI flows (preferred).