Browse tech roles

TCL Python Perl UPF CPF LEC MCMM_STA DFT SerDes PCIe CXL C2C Die-to-Die RTL-to-GDSII CTS EMIR ECO EDA_tool_suites automation_scripting +14 more Show less

Python Perl Make Shell_scripting AI_frameworks RTL Functional_verification Formal_verification Physical_design CI/CD EDA_tools Kubernetes Docker Terraform AWS Grafana Prometheus +12 more Show less

Python Verilog C++ UPF DVFS multi-VT clock gating power gating voltage islands Power Estimation SW-driven power virus tests silicon debug Power Supply Analysis Oscilloscopes DAQs +10 more Show less

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow +6 more Show less

Verilog RTL ASIC VLSI Digital systems Computer Architecture Computer Arithmetic Low-power design Logic synthesis Timing analysis Arbiters Scheduling Synchronization Bus protocols Interconnect networks Dataflow architectures CPU subsystems +12 more Show less